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MC14561BALDS

更新时间： 2024-02-03 17:24:36
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 运算电路逻辑集成电路输出元件编码器
页数 文件大小 规格书
8页 181K
描述
4000/14000/40000 SERIES, 4-BIT ENCODER, CDIP14, 632-08

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MC14561BALDS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
JESD-30 代码：R-XDIP-T14JESD-609代码：e0
逻辑集成电路类型：ENCODER端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Arithmetic Circuits表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC14561BALDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14561B 9’s complementer is a companion to the MC14560B  
NBCD adder to allow BCD subtraction. A BCD number (8–4–2–1 code) is  
0
1
2
3
applied to the inputs (A1 = 2 , A2 = 2 , A3 = 2 , A4 = 2 ). If the complement  
control (Comp) is low, the BCD number appears at the outputs unmodified.  
The complement disable (Comp) allows the complement control to be gated,  
or an inverted control signal to be used. If the complement input is high and  
the disable input low, the 9’s complement of the number is displayed at the  
outputs. The zero control (Z), when high, forces the outputs low regardless of  
the state of the other inputs.  
When the MC14561B is used to perform BCD subtraction in conjunction  
with the MC14560B NBCD adder, the complement control becomes an  
add/subtract control.  
P SUFFIX  
PLASTIC  
CASE 646  
D SUFFIX  
SOIC  
CASE 751A  
•
•
•
All Inputs Buffered  
ORDERING INFORMATION  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
PIN ASSIGNMENT  
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
A1  
A2  
A3  
A4  
1
2
3
4
14  
13  
12  
11  
V
DD  
in out  
I , I  
F1  
F2  
F3  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
– 65 to + 150  
260  
mW  
C
T
stg  
COMP  
COMP  
5
6
10  
9
F4  
Z
T
L
Lead Temperature (8–Second Soldering)  
C
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
V
7
8
NC  
SS  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
NC = NO CONNECTION  
TRUTH TABLE  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
Z
0
0
Comp Comp F1  
F2  
F3  
F4  
Mode  
0
0
0
1
A1  
A2  
A3  
A4  
Straight–through  
0
0
1
1
1
1
0
operation, V and V  
to the range V  
SS  
Unused inputs must always be tied to an  
should be constrained  
in  
out  
(V or V  
)
V
DD  
.
A1  
0
A2 A2A3 + A2A3 A2A3A4  
Complement  
Zero  
in out  
X
X
0
0
0
appropriate logic voltage level (e.g., either V  
SS  
or V ). Unused outputs must be left open.  
X = Don’t Care.  
DD  
REV 3  
1/94  
Motorola, Inc. 1995  
12345678

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