MITSUBISHI DIGITAL ASSP
MITSUBISHI DIGITAL ASSP
M660M0676P00/7FPP/FP
12-BIT INPUT EXPANDER
12-BIT INPUT EXPANDER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M66007 is a semiconductor integrated circuit providing
the 12-bit parallel input-serial output shift register function.
This product is completely designed with CMOS to sharply
reduce power consumption compared with bipolar or Bi-
CMOS product.
The M66007, developed as an input only expander IC neces-
sary for microcomputer periphery, is widely applicable as a
data parallel/serial conversion IC.
LATCH INPUT/
SERIAL DATA OUTPUT
↔
→
→
→
→
→
→
LE/D
1
2
3
4
5
6
7
8
LE/D
16
15
14
13
12
11
10
9
VCC
←
←
←
←
←
←
←
CLOCK INPUT CLK
D0
CLK D11
D11
D10
D9
D0
D1
D2
D3
D4
D10
D9
D8
D7
D6
D5
D1
PARALLEL
DATA INPUT
PARALLEL
DATA INPUT
D2
D8
D3
D4
D7
FEATURES
D6
• Control signals of only two pins including LE/D and CLK
• Low power consumption of 50 µW/package maximum
(Vcc=5V, Ta=25°C at time of standstill)
GND
D5
• Schmitt triggered input (LE/D, CLK, D0 to D11)
• Wide operating supply voltage range (Vcc=2~6V)
• Wide operating temperature range (Ta=–20~75°C)
Outline 16P4
16P2N-A
APPLICATION
Parallel/serial data conversion for microcomputer periphery
After this, change of CLK from “H” to “L” makes the shift regis-
ter perform shift operation and LE/D outputs the contents of
the shift register from D0 in order.
FUNCTION
The M66007 uses a silicon gate CMOS process to achieve
low power consumption and high noise margin.
For control signals, this IC adopts only the two pins of latch
input/serial data output LE/D and clock input CLK. Each bit
of shift register of 12-bit parallel input-serial output consists of
flip-flop for shift.
In addition, the shift operation for up to the 12th bit is carried
out and then LE/D is switched to the input mode at the falling
edge of CLK of the 13th bit.
When power is turned on, the input/output mode of LE/D is
indeterminate. However, detection of 13 or more falling
edges of CLK sets LE/D in the input mode.
When LE/D is placed in input mode, CLK is set to “H” and LE/
D changes from “H” to “L”, the status of parallel data inputs D0
to D11 at that time is latched with the flip-flop for shift and LE/
D is switched to output mode to output “L”.
BLOCK DIAGRAM
Vcc
QP
LATCH INPUT/
SERIAL DATA OUTPUT
CONTROL CIRCUIT
SD
LE
1
2
LE/D
LCLK
Q
N
SQ
CLOCK INPUT CLK
SHIFT REGISTER
CLK
D11
D10
D9
D8
D0
Q
11
11
Q
10
Q
9
Q
8
Q0
16
8
Vcc
LE
PARALLEL LATCH
GND
D
D
10
D
9
D
8
D7
D6
D5
D4
D3
D2
D1
D0
15
13 12 11 10
9
6
5
4
3
14
7
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D
1
D0
PARALLEL DATA INPUT
1