+/+…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
Preliminary
Product Features
•
•
•
•
Dedicated clock buffer power pins for reduced
noise, crosstalk and jitter
Test Mode Logic Table
INPUT PINS
OUTPUT PINS
Buffer XIN Reference clock output
OEA
OEB
SA1
SB1
LOW
LOW
HIGH
HIGH
X
SA0
SB0
CLKA(0:4)
REF
Input clock frequency 33.3 MHz
Reference may be a clock or a crystal
CLKB(0:4)
XIN
HIGH
HIGH
HIGH
HIGH
LOW
LOW
XIN
XIN
HIGH
LOW
HIGH
X
2 X XIN
3 X XIN
4 X XIN
Tri-State
•
Output frequencies of 33.3, 66.6, 100 and 133.3
MHz selectable (PCIX requirements)
XIN
XIN
•
•
Output grouped in two banks of 5 clocks each.
I2C clock control interface for individual clock
disabling, SSCG control and individual bank
frequency selection
Tri-State
Note: A and B banks have separate frequency select
and output enable controls. XIN is the frequency of
the clock on the device’s XIN pin. OEA or OEB will
tristate REF.
•
•
Output clock duty cycle is 50% (± 5%)
<250 pS skew between output clocks within a
bank
•
Output jitter <250 pSec. (175pSec with all
outputs at the same frequency)
Pin Configuration
•
•
Spread Spectrum feature for reduced EMI
OE pins for separate output bank enable control
and testability
48
REF
VDD
1
SDATA
SCLK
VDD
2
47
46
45
44
•
48 Pin SSOP and TSSOP package
XIN
3
XOUT
VSS
4
VSS
Block Diagram
5
VDD
SA0
6
SB0
43
42
41
SA1
7
SB1
VSS
8
VSS
AGOOD#
CLKA0
CLKA1
VDDA
CLKA2
VSS
9
CLKB0
CLKB1
VDDB
CLKB2
VSS
40
39
38
37
10
11
12
13
14
15
16
17
18
19
20
SSCG
Logic
CLKA0
CLKA1
SSCG#
/N
1
0
36
35
34
33
CLKA2
CLKA3
CLKA4
VDDA
CLKA3
CLKA4
VSS
VDDB
CLKB3
CLKB4
VSS
XIN
OEA
32
31
30
29
28
AGOOD#
VSS
BGOOD#
AVDD
AVDD
VSS
CLKB0
XOUT
CLKB1
CLKB2
CLKB3
CLKB4
0
1
IA0
IA1
21
22
23
24
/N
SDATA
27
26
25
IA2
SSCG#
VSS
AVDD
OEA
SCLK
I2C
Control
Logic
OEB
OEB
IA(0:2)
SA(0,1)
SB(0,1)
BGOOD#
REF
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
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