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9P936AFLFT PDF预览

9P936AFLFT

更新时间: 2024-01-15 22:13:34
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
12页 190K
描述
Low Skew Dual Bank DDR I/II Fan-out Buffer

9P936AFLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:N系列:5V
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.03 A
湿度敏感等级:1功能数量:1
反相输出次数:1端子数量:28
实输出次数:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:1.8/2.5 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.04 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

9P936AFLFT 数据手册

 浏览型号9P936AFLFT的Datasheet PDF文件第4页浏览型号9P936AFLFT的Datasheet PDF文件第5页浏览型号9P936AFLFT的Datasheet PDF文件第6页浏览型号9P936AFLFT的Datasheet PDF文件第8页浏览型号9P936AFLFT的Datasheet PDF文件第9页浏览型号9P936AFLFT的Datasheet PDF文件第10页 
ICS9P936  
Low Skew Dual Bank DDR I/II Fan-out Buffer  
Timing Requirements VDDQ2.5/1.8 = 2.5V +/- 0.2V  
TA = 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated)  
SPECIFICATION  
PARAMETER  
Max clock frequency  
Application Frequency Range  
Input clock duty cycle  
CLK stabilization  
SYMBOL  
freqop  
freqApp  
dtin  
CONDITIONS  
MIN  
45  
MAX  
500  
233  
60  
UNITS  
MHz  
MHz  
%
95  
40  
TSTAB  
15  
µs  
Switching Characteristics (VDDQ2.5/1.8 = 2.5V +/- 0.2V )  
(see note 1)  
TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 2.5 V +/- 0.2V (unless otherwise stated)  
SPECIFICATION  
PARAMETER  
Period jitter  
SYMBOL  
Tjit (per)  
CONDITION  
Period jitter  
MIN  
-60  
-75  
-60  
-50  
TYP  
0
MAX UNITS  
60  
75  
60  
50  
40  
53  
ps  
ps  
ps  
ps  
ps  
ps  
Half-period jitter  
T(jit_hper)  
Half period jitter  
Cycle to Cycle Jitter  
Static Phase Offset  
Output to Output Skew  
Output Duty Cycle  
T
cyc-Tcyc  
T(SPO)  
Tskew  
tduty  
Cycle to Cycle jitter  
DDR(0:5)  
47  
Measured from 20% to 80% of  
VDDQ  
Output clock slew rate  
tsl(o)  
1.5  
4
V/ns  
1. Switching characteristics guaranteed for operating frequency range  
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer  
1084C 12/03/09  
7

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