Datasheet > 9FGU0231

9FGU0231

更新时间： 2022-02-26 10:49:51

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
15页	197K
描述
2 O/P 1.5V PCIe Gen1-2-3 Clock Generator

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9FGU0231 数据手册

9FGU0231 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

TA = T_AMB;Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

Supply Voltage

SYMBOL

VDDxx

CONDITIONS

MIN

TYP

1.5

MAX

UNITS NOTES

Supply voltage for core, analog and single-ended

LVCMOS outputs

1.425

1.575

Ambient Operating

Temperature

Comercial range

°C

T_AMB

Industrial range

-40

Input High Voltage

Input Mid Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

V_IH

V_IM

V_IL

V_IH

V_IL

I_IN

Single-ended inputs, except SMBus

Single-ended tri-level inputs ('_tri' suffix)

Single-ended inputs, except SMBus

0.75 V_DD

0.4 V_DD

-0.3

V_DD+ 0.3

0.5 V_DD0.6 V_DD

0.25 V_DD

Single-ended outputs, except SMBus. I_OH= -2mA V_DD-0.45

Single-ended outputs, except SMBus. I_OL= -2mA

0.45

Single-ended inputs, V_IN= GND, V_IN= VDD

Single-ended inputs

_IN= 0 V; Inputs with internal pull-up resistors

_IN= VDD; Inputs with internal pull-down resistors

XTAL, or X1 input

-5

-200

Input Current

I_INP

200

Input Frequency

Pin Inductance

F_in

L_pin

MHz

C_IN

Logic Inputs, except DIF_IN

Output pin capacitance

1.5

Capacitance

C_OUT

From V_DDPower-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

Triangular Modulation

Clk Stabilization

T_STAB

1.8

1,2

SS Modulation Frequency

OE# Latency

f_MOD

31.6

kHz

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

t_LATOE#

clocks

1,3

Tdrive_PD#

t_DRVPD

300

1,3

PD# de-assertion

Tfall

t_F

Fall time of single-ended control inputs

Trise

t_R

Rise time of single-ended control inputs

SMBus Input Low Voltage

SMBus Input High Voltage

V_ILSMB

V_IHSMB

0.6

3.3

0.4

V_DDSMB= 3.3V, see note 4 for V_DDSMB< 3.3V

2.1

SMBus Output Low Voltage V_OLSMB

@ I_PULLUP

@ V_OL

SMBus Sink Current

Nominal Bus Voltage

SCLK/SDATA Rise Time

I_PULLUP

V_DDSMB

t_RSMB

1.425

3.3

1000

300

(Max VIL - 0.15) to (Min VIH + 0.15)

(Min VIH + 0.15) to (Max VIL - 0.15)

SCLK/SDATA Fall Time

SMBus Operating

Frequency

t_FSMB

f_MAXSMB

Maximum SMBus operating frequency

400

kHz

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are >200 mV

⁴For V_DDSMB< 3.3V, V_IHSMB>= 0.8xV_DDSMB

2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

OCTOBER 18, 2016

1...3 4 567 8 9...15

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