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9DB403DFILF

更新时间： 2024-02-22 16:07:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
19页 278K
描述
Four Output Differential Buffer for PCIe Gen 1 and Gen 2

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9DB403DFILF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP28,.25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.11
系列：9DB输入调节：DIFFERENTIAL MUX
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
长度：9.7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：4最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP28,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

9DB403DFILF 数据手册

 浏览型号9DB403DFILF的Datasheet PDF文件第3页浏览型号9DB403DFILF的Datasheet PDF文件第4页浏览型号9DB403DFILF的Datasheet PDF文件第5页浏览型号9DB403DFILF的Datasheet PDF文件第7页浏览型号9DB403DFILF的Datasheet PDF文件第8页浏览型号9DB403DFILF的Datasheet PDF文件第9页 
ICS9DB403D  
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2  
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = Tambient for the desired operating range, Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
Input High Voltage  
Input Low Voltage  
Input High Current  
SYMBOL  
VIHSE  
VILSE  
CONDITIONS  
Single Ended Inputs, 3.3 V +/-5%  
VIN = VDD  
MIN  
TYP  
MAX  
VDD + 0.3  
0.8  
UNITS NOTES  
2
GND - 0.3  
-5  
V
V
1
1
1
IIHSE  
5
uA  
IIL1  
IIL2  
VIN = 0 V; Inputs with no pull-up resistors  
-5  
uA  
uA  
1
1
1
Input Low Current  
VIN = 0 V; Inputs with pull-up resistors  
Full Active, CL = Full load; Commerical  
Temp Range  
Full Active, CL = Full load; Industrial Temp  
-200  
IDD3.3OPC  
175  
190  
200  
225  
mA  
9DB803 Supply Current  
IDD3.3OPI  
IDD3.3PDC  
IDD3.3PDI  
IDD3.3OPC  
IDD3.3OPI  
IDD3.3PDC  
IDD3.3PDI  
mA  
1
Range  
all diff pairs driven, C-Temp  
all differential pairs tri-stated, C-Temp  
all diff pairs driven, I-temp  
all differential pairs tri-stated, I-temp  
Full Active, CL = Full load; Commerical  
50  
4
55  
6
60  
6
65  
8
mA  
mA  
mA  
mA  
1
1
1
1
9DB803 Powerdown  
Current  
105  
115  
125  
150  
mA  
mA  
1
1
Temp Range  
Full Active, CL = Full load; Industrial Temp  
9DB403 Supply Current  
Range  
all diff pairs driven, C-Temp  
all differential pairs tri-stated, C-Temp  
all diff pairs driven, I-Temp  
all differential pairs tri-stated, I-Temp  
PCIe Mode (Bypass#/PLL= 1)  
25  
2
30  
30  
3
35  
4
110  
400  
7
mA  
mA  
mA  
mA  
MHz  
MHz  
nH  
1
1
1
1
1
1
1
9DB403 Powerdown  
Current  
3
FiPLL  
FiBYPASS  
Lpin  
50  
33  
100.00  
Input Frequency  
Pin Inductance  
Bypass Mode ((Bypass#/PLL= 0)  
CIN  
CINSRC_IN  
COUT  
Logic Inputs, except SRC_IN  
SRC_IN differential clock inputs  
Output pin capacitance  
1.5  
1.5  
5
2.7  
6
pF  
pF  
pF  
1
1,4  
1
Capacitance  
-3dB point in High BW Mode  
-3dB point in Low BW Mode  
Peak Pass band Gain  
2
0.7  
3
1
1.5  
4
1.4  
2
MHz  
MHz  
dB  
1
1
1
PLL Bandwidth  
BW  
tJPEAK  
PLL Jitter Peaking  
From VDD Power-Up and after input clock  
TSTAB  
Clk Stabilization  
1
ms  
1,2  
stabilization or de-assertion of PD# to 1st  
clock  
Input SS Modulation  
Frequency  
Allowable Frequency  
fMODIN  
tLATOE#  
tDRVSTP  
tDRVPD  
30  
1
33  
3
kHz  
cycles  
ns  
1
(Triangular Modulation)  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
SRC_Stop# de-assertion  
DIF output enable after  
PD# de-assertion  
OE# Latency  
Tdrive_SRC_STOP#  
Tdrive_PD#  
1,3  
1,3  
1,3  
10  
300  
us  
tF  
tR  
VMAX  
VOL  
Tfall  
Trise  
Fall time of PD# and SRC_STOP#  
5
5
5.5  
0.4  
ns  
ns  
V
V
mA  
1
2
1
1
1
Rise time of PD# and SRC_STOP#  
Maximum input voltage  
@ IPULLUP  
SMBus Voltage  
Low-level Output Voltage  
Current sinking at VOL  
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
Clock/Data Fall Time  
SMBus Operating  
Frequency  
IPULLUP  
4
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
tRSMB  
tFSMB  
1000  
300  
ns  
ns  
1
1
fMAXSMB  
Maximum SMBus operating frequency  
100  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2See timing diagrams for timing requirements.  
3Time from deassertion until outputs are >200 mV  
4SRC_IN input  
5The differential input clock must be running for the SMBus to be active  
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2  
ICS9DB403D  
REV L 10/07/09  
6
1...3456789...19

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