97SD3248BRPQI

更新时间： 2024-01-11 11:16:54

品牌	Logo	应用领域
麦斯威 - MAXWELL		动态存储器
页数	文件大小	规格书
40页	583K
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97SD3248BRPQI 数据手册

97SD3248

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM

TABLE 5. AC Electrical Characteristics

(V =3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

SUBGROUPS

MIN

TYPICAL

MAX

UNIT

System clock cycle time¹

t_CK

9, 10, 11

(CAS latency = 2)

(CAS latency = 3)

7.5

CLK high pulse width^1,7

CLK low pulse width^1,7,

t_CKH

t_CKL

t_AC

9, 10, 11

2.5

1,2

Access time from CLK

(CAS latency = 2)

(CAS latency = 3)

Data-out hold time^1,2,3

CLK to Data-out low impedance^1,2,3,7

CLK to Data-out high impedance^1,47,

(CAS latency = 2, 3)

t_OH

t_LZ

9, 10, 11

2.7

t_HZ

5.4

Input setup time^1,5,6

t_AS, t_CS,

t_DS, t_CES

9, 10, 11

1.5

CKE setup time for power down exit¹

Input hold time^1,6

t_CESP

9, 10, 11

1.5

t_AH, t_CH, t_DH

t_CEH

Ref/Active to Ref/Active command period¹

Active to Precharge command period¹

Active command to column command ¹

(same bank)

t_RC

t_RAS

t_RCD

9, 10, 11

120000

Precharge to Active command period¹

t_RP

t_DPL

t_RRD

t_T

9, 10, 11

@ 105 °C

@ 85 °C

@ 70 °C

Write recovery or data-in to precharge lead time¹

Active( a) to Active (b) command period¹

Transition time(rise and fall)⁷

Refresh Period

t_REF

6.4

16⁸

128

1. AC measurement assumes t_T=1ns. Reference level for timing of input signals is 1.5V.

2. Access time is measured at 1.5V.

3. t_LZ(min) definesthe time at which the outputs achieve the low impedance state.

4. t_HZ(min) defines the time at which the outputs achieve the high impedance state.

5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.

6. t_AS/t_AH: Address, t_CS/t_CH: /RAS, /CAS, /WE, DQM

7. Guarenteed by design (Not tested).

8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)

02.04.05 Rev 3

All data sheets are subject to change without notice

1 2 3 456 7 8...40

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