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97SD3232RPMK PDF预览

97SD3232RPMK

更新时间: 2024-02-24 22:52:52
品牌 Logo 应用领域
麦斯威 - MAXWELL 动态存储器
页数 文件大小 规格书
39页 745K
描述
1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks

97SD3232RPMK 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.84

97SD3232RPMK 数据手册

 浏览型号97SD3232RPMK的Datasheet PDF文件第1页浏览型号97SD3232RPMK的Datasheet PDF文件第2页浏览型号97SD3232RPMK的Datasheet PDF文件第3页浏览型号97SD3232RPMK的Datasheet PDF文件第5页浏览型号97SD3232RPMK的Datasheet PDF文件第6页浏览型号97SD3232RPMK的Datasheet PDF文件第7页 
97SD3232  
1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM  
TABLE 4. DC ELECTRICAL CHARACTERISTICS  
(V = 3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)  
CC  
CC  
A
PARAMETER  
SYMBOL  
TEST CONDITIONS  
SUBGROUPS  
MIN  
MAX  
UNITS  
Standby Current in non power down6  
ICC2N  
ICC2NS  
ICC3P  
CKE, CS = V  
tCK = 12 ns  
1, 2, 3  
80  
mA  
IH  
Standby Current in non power down7  
( Input signal stable)  
Active standby current in1,2,4  
power down  
CKE = V  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
36  
16  
mA  
mA  
mA  
mA  
mA  
mA  
IH  
tCK = 0  
CKE = V  
IL  
tCK = 12 ns  
Active standby current in power down  
(input signal stable)2,5  
ICC3PS  
ICC3N  
ICC3NS  
ICC4  
CKE = V  
12  
IL  
tCK = 0  
Active standby power in non power  
down1,2,6  
CKE, CS1-4 = V  
120  
60  
IH  
tCK = 12 ns  
Active standby current in non power  
down ( input signal stable)2,7  
Burst Operating Current1,2,8  
CAS Latency = 2  
CKE = V  
IH  
tCK = 0  
tCK = min  
BL = 4  
440  
580  
CAS Latency = 3  
Refresh Current3  
Self Refresh current9  
ICC5  
ICC6  
tRC = min  
1, 2, 3  
1, 2, 3  
880  
12  
mA  
mA  
V >V - 0.2V  
IH CC  
V < 0.2 V  
IL  
Input Leakage Current - CLK  
Input Leakage Current - All Other  
Output Leakage Current  
Output high voltage  
ILI  
ILI  
0<V <V  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
-2  
-4  
2
4
uA  
uA  
uA  
V
LI CC  
0<V <V  
LI CC  
ILO  
0<V <V  
-1.5  
2.4  
1.5  
LO CC  
V
IOH = -4mA  
OH  
Output low voltage  
V
IOL = 4 mA  
0.4  
V
OL  
1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open.  
2. One Bank Operation  
3. Input signals are changed once per clock.  
4. After power down mode, CLK operating current.  
5. After power down mode, no CLK operating current.  
6. Input signals are changed once per two clocks.  
7. Input signals for VIH or VIL are fixed.  
8. Input signals are changed once per four clocks.  
9. After self refresh mode set, self refresh current. Use Self Refresh for temperatures less than 70 °C ONLY  
01.11.05 Rev 2  
All data sheets are subject to change without notice  
4
©2005 Maxwell Technologies  
All rights reserved.  

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