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954204CG PDF预览

954204CG

更新时间： 2024-01-18 10:35:32
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 199K
描述
Clock Generator

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954204CG 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：,Reach Compliance Code：not_compliant
风险等级：5.91JESD-609代码：e0
湿度敏感等级：1端子面层：Tin/Lead (Sn85Pb15)
Base Number Matches：1

954204CG 数据手册

 浏览型号954204CG的Datasheet PDF文件第1页浏览型号954204CG的Datasheet PDF文件第3页浏览型号954204CG的Datasheet PDF文件第4页浏览型号954204CG的Datasheet PDF文件第5页浏览型号954204CG的Datasheet PDF文件第6页浏览型号954204CG的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS954204  
Systems, Inc.  
Pin Description  
PIN # PIN NAME  
PIN TYPE DESCRIPTION  
1
VDDPCI  
GND  
PCICLK3  
PCICLK4  
PCICLK5  
GND  
PWR  
PWR  
OUT  
OUT  
OUT  
PWR  
PWR  
Power supply for PCI clocks, nominal 3.3V  
Ground pin.  
PCI clock output.  
PCI clock output.  
PCI clock output.  
Ground pin.  
Power supply for PCI clocks, nominal 3.3V  
Free running PCI clock not affected by PCI_STOP#.  
ITP_EN: latched input to select pin functionality  
1 = CPU_ITP pair  
2
3
4
5
6
7
VDDPCI  
8
ITP_EN/PCICLK_F0  
I/O  
I/O  
IN  
0 = SRC pair  
Latched input select for LCD_ss/ SRCCLK output frequency:  
0 = LCD,  
1 = SRCCLK/ 3.3V free-running PCI clock output.  
Vtt_PwrGd# is an active low input used to determine when latched inputs  
are ready to be sampled. PD is an asynchronous active high input pin used  
to put the device into a low power state. The internal clocks, PLLs and the  
crystal oscillator are stopped.  
9
*SELSRC_LCDCLK#/PCICLK_F1  
Vtt_PwrGd#/PD  
10  
11  
12  
VDD48  
PWR  
I/O  
Power pin for the 48MHz output.3.3V  
3.3V tolerant input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock  
output. 3.3V.  
FSLA/USB_48MHz  
13  
14  
15  
GND  
DOTT_96MHz  
DOTC_96MHz  
PWR  
OUT  
OUT  
Ground pin.  
True clock of differential pair for 96.00MHz DOT clock.  
Complement clock of differential pair for 96.00MHz DOT clock.  
3.3V tolerant input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time  
input to select between Hi-Z and REF/N divider mode while in test mode.  
Refer to Test Clarification Table.  
16  
FSLB/TEST_MODE  
IN  
True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.  
Selected by SEL_LCDCLK#  
Complementary clock of LCDCLK_SS output / Complementary clock of  
SRCCLK differential pair. Selected by SEL_LCDCLK#  
True clock of differential SRC clock pair.  
Complement clock of differential SRC clock pair.  
Supply for SRC clocks, 3.3V nominal  
True clock of differential SRC clock pair.  
Complement clock of differential SRC clock pair.  
True clock of differential SRC clock pair.  
Complement clock of differential SRC clock pair.  
True clock of differential SRC/SATA pair.  
Complement clock of differential SRC/SATA pair.  
Supply for SRC clocks, 3.3V nominal  
17  
18  
LCDCLK_SST/SRCCLKT0  
LCDCLK_SSC/SRCCLKC0  
OUT  
OUT  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
SRCCLKT1  
SRCCLKC1  
VDDSRC  
SRCCLKT2  
SRCCLKC2  
SRCCLKT3  
SRCCLKC3  
SRCCLKT4_SATA  
SRCCLKC4_SATA  
VDDSRC  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
PWR  
0933D—03/16/05  
2
1234567...16

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