Integrated
Circuit
ICS952607
Systems, Inc.
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
5
6
7
8
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
I/O
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
14.318 MHz reference clock.
OUT
PWR
IN
OUT
PWR
I/O
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
^^PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
9
I/O
10
11
12
13
14
15
16
17
18
19
20
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCICLK4
PCICLK5
PCI clock output.
21
**Sel24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 = 48MHz.
22
23
24
25
26
27
28
29
30
31
32
33
**FS3/48MHz_0
48MHz_1
GND
VDD48
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
48MHz clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
SDATA
I/O
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active high input. / Asynchronous active low
input pin used to power down the device into a low power state.
34
VttPWR_GD/PD#
IN
35
36
VDD
PWR
OUT
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
SRCCLKC
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
37
38
39
SRCCLKT
GND
OUT
PWR
OUT
CPUCLKC0
40
41
42
CPUCLKT0
VDDCPU
OUT
PWR
OUT
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
CPUCLKC1
43
44
45
CPUCLKT1
GND
OUT
PWR
OUT
Ground pin.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
Reset#
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Ground pin.
46
IREF
OUT
47
48
GND
VDDA
PWR
PWR
3.3V power for the PLL core.
0734A—07/26/05
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