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93LC46-ISN PDF预览

93LC46-ISN

更新时间: 2024-01-12 16:21:39
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 176K
描述
1K/2K/4K 2.0V Microwire Serial EEPROM

93LC46-ISN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51Factory Lead Time:9 weeks
风险等级:5.24Is Samacsys:N
其他特性:3 WIRE INTERFACE; AUTOMATIC WRITE; ERAL AT 4.5V TO 6.0V备用内存宽度:8
最大时钟频率 (fCLK):2 MHz数据保留时间-最小值:200
耐久性:1000000 Write/Erase CyclesJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
内存密度:1024 bit内存集成电路类型:EEPROM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:8
字数:64 words字数代码:64
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64X16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.75 mm
串行总线类型:MICROWIRE最大待机电流:0.00003 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
最长写入周期时间 (tWC):10 ms写保护:SOFTWARE
Base Number Matches:1

93LC46-ISN 数据手册

 浏览型号93LC46-ISN的Datasheet PDF文件第2页浏览型号93LC46-ISN的Datasheet PDF文件第3页浏览型号93LC46-ISN的Datasheet PDF文件第4页浏览型号93LC46-ISN的Datasheet PDF文件第6页浏览型号93LC46-ISN的Datasheet PDF文件第7页浏览型号93LC46-ISN的Datasheet PDF文件第8页 
93LC46/56/66  
3.2  
Data In (DI) and Data Out (DO)  
3.0  
FUNCTIONAL DESCRIPTION  
When it is connected to ground, the (x8) organization is  
selected. When the ORG pin is connected to Vcc, the  
(x16) organization is selected. Instructions, addresses  
and write data are clocked into the DI pin on the rising  
edge of the clock (CLK).The DO pin is normally held in  
a HIGH-Z state, except when reading data from the  
device or when checking the READY/BUSY status dur-  
ing a programming operation. The READY/BUSY  
status can be verified during an ERASE/WRITE opera-  
tion by polling the DO pin; DO low indicates that pro-  
gramming is still in progress, while DO high indicates  
the device is ready. The DO will enter the HIGH-Z state  
on the falling edge of the CS.  
It is possible to connect the Data In (DI) and Data Out  
(DO) pins together. However, with this configuration, if  
A0 is a logic-high level, it is possible for a “bus conflict”  
to occur during the “dummy zero” that precedes the  
READ operation. Under such a condition the voltage  
level seen at DO is undefined and will depend upon the  
relative impedances of Data Out, and the signal source  
driving A0.The higher the current sourcing capability of  
A0, the higher the voltage at the DO pin.  
3.3  
Data Protection  
During power-up, all programming modes of operation  
are inhibited until Vcc has reached a level greater than  
1.4V. During power-down, the source data protection  
circuitry acts to inhibit all programming modes when  
Vcc has fallen below 1.4V at nominal conditions.  
3.1  
START Condition  
The START bit is detected by the device if CS and DI  
are both high with respect to the positive edge of CLK  
for the first time.  
The ERASE/WRITE Disable (EWDS) and ERASE/  
WRITE Enable (EWEN) commands give additional pro-  
tection against accidentally programming during nor-  
mal operation.  
Before a START condition is detected, CS, CLK, and DI  
may change in any combination (except to that of a  
START condition), without resulting in any device oper-  
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,  
and WRAL). As soon as CS is high, the device is no  
longer in the standby mode.  
After power-up, the device is automatically in the  
EWDS mode. Therefore, an EWEN instruction must be  
performed before any ERASE or WRITE instruction can  
be executed.  
An instruction following a START condition will only be  
executed if the required amount of opcodes,  
addresses, and data bits for any particular instruction is  
clocked in.  
After execution of an instruction (i.e., clock in or out of  
the last required address or data bit) CLK and DI  
become don't care bits until a new START condition is  
detected.  
FIGURE 3-1: SYNCHRONOUS DATA TIMING  
VIH  
CS  
TCSS  
TCKH  
TCKL  
VIL  
TCSH  
VIH  
CLK  
DI  
VIL  
TDIH  
TDIS  
VIH  
VIL  
TCZ  
TPD  
TPD  
VOH  
DO  
(READ)  
TCZ  
VOL  
VOH  
TSV  
DO  
(PROGRAM)  
STATUS VALID  
VOL  
1997 Microchip Technology Inc.  
DS11168L-page 5  

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