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9301-11

更新时间： 2024-01-28 06:07:38
品牌 Logo 应用领域
PSEMI 预分频器
页数 文件大小 规格书
7页 228K
描述
3500 MHz Low Power UltraCMOS Divide-by-2 Prescaler Rad-hard for Space Applications

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9301-11 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：LSOP, SOP8,.4针数：8
Reach Compliance Code：compliant风险等级：5.62
系列：9301JESD-30 代码：S-CDSO-G8
逻辑集成电路类型：PRESCALER最大频率@ Nom-Sup：3500000000 Hz
数据/时钟输入次数：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：LSOP
封装等效代码：SOP8,.4封装形状：SQUARE
封装形式：SMALL OUTLINE电源：3 V
最大电源电流（ICC）：15 mA认证状态：Not Qualified
座面最大高度：1.57 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：3.15 V最小供电电压 (Vsup)：2.85 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

9301-11 数据手册

 浏览型号9301-11的Datasheet PDF文件第1页浏览型号9301-11的Datasheet PDF文件第3页浏览型号9301-11的Datasheet PDF文件第4页浏览型号9301-11的Datasheet PDF文件第5页浏览型号9301-11的Datasheet PDF文件第6页浏览型号9301-11的Datasheet PDF文件第7页 
PE9301  
Product Specification  
Figure 3. Pin Configuration  
Electrostatic Discharge (ESD) Precautions  
When handling this UltraCMOS™ device, observe  
the same precautions that you would use with  
other ESD-sensitive devices. Although this device  
contains circuitry to protect it from damage due to  
ESD, precautions should be taken to avoid  
exceeding the rating specified in Table 3.  
VDD  
1
8
7
6
5
GND  
OUT  
2
3
4
IN  
PE9301  
DEC  
GND  
NC  
GND  
Latch-Up Avoidance  
Unlike conventional CMOS devices, UltraCMOS™  
devices are immune to latch-up.  
Table 2. Pin Descriptions  
Device Functional Considerations  
Pin  
Pin No.  
Description  
Name  
The PE9301 takes an input signal frequency from  
between 1.5 GHz to 3.5 GHz and produces an  
output signal frequency half that of the supplied  
input. In order for the prescaler to work properly,  
several conditions need to be adhered to. It is  
crucial that pin 3 be supplied with a bypass  
capacitor to ground. In addition, the input and  
output signals (pins 2 & 7, respectively) need to  
be AC coupled via an external capacitor as shown  
in Figure 5.  
1
2
VDD  
IN  
Power supply pin. Bypassing is required.  
Input signal pin. Should be coupled with a  
capacitor (eg 15 pF).  
Power supply decoupling pin. Place a  
capacitor as close as possible and connect  
directly to the ground plane.  
3
4
DEC  
GND  
Ground pin. Ground pattern on the board  
should be as wide as possible to reduce  
ground impedance.  
5
6
GND  
NC  
Ground pin.  
The ground pattern on the board should be made  
as wide as possible to minimize ground  
impedance.  
No connection. This pin should be left  
open.  
Divided frequency output pin. This pin  
should be coupled with a capacitor  
(eg 47 pF).  
7
8
OUT  
GND  
Ground Pin.  
Table 3. Absolute Maximum Ratings  
Symbol  
VDD  
Parameter/Conditions Min Max Units  
Supply voltage  
4.0  
V
TST  
Storage temperature range  
-65  
-40  
150  
°C  
Operating temperature  
range  
TOP  
85  
°C  
V
ESD voltage (Human Body  
Model)  
VESD  
250  
Absolute Maximum Ratings are those values  
listed in the above table. Exceeding these values  
may cause permanent device damage.  
Functional operation should be restricted to the  
limits in the DC Electrical Specifications table.  
Exposure to absolute maximum ratings for  
extended periods may affect device reliability.  
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0039-02 │ UltraCMOS™ RFIC Solutions  
Page 2 of 7  
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