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9179YG-03LF-T PDF预览

9179YG-03LF-T

更新时间: 2024-09-30 20:49:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 273K
描述
Low Skew Clock Driver, 9179 Series, 10 True Output(s), 0 Inverted Output(s), PDSO28, 6.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28

9179YG-03LF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66系列:9179
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:28
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):5.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mm最小 fmax:133 MHz
Base Number Matches:1

9179YG-03LF-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9179-03  
Low Skew Fan Out Buffers  
General Description  
Features  
Ten High speed, low noise non-inverting buffers for (to  
133MHz), clockbufferapplications.  
Output slew rate faster than 1.5V/ns into 20pF  
Supports up to four small outline DIMMS (S.O. DIMM).  
The ICS9179-03 generates low skew clock buffers required  
for high speed RISC or CISC microprocessor systems such as  
Intel PentiumPro. Outputs will handle up to 133MHz clocks.  
An output enable is provided for testability.  
Synchronous clocks skew matched to 250ps window on  
OUTPUTs(0:9).  
The device is a buffer with low output to output skew. This is  
a Fanout buffer device, not using an internal PLL. This buffer  
can also be a feedback to an external PLL stage for phase  
synchronization to a master clock. There are a total of ten  
outputs, sufficient for feedback to a PLL source and to drive  
four small outline DIMM modules (S.O. DIMM) at 2 clocks  
each. Or a total of ten outputs as a Fanout buffer from a  
common clock source.  
I2C Serial Configuration interface to allow individual  
OUTPUTs to be stopped low.  
Multiple VDD, VSS pins for noise reduction  
Tri-state pin for testing  
3.0V – 3.7V supply range  
28-pin(209mil)SSOPand(6.1mm)TSSOPpackage  
The individual clock outputs are addressable through I2C to  
be enabled, or stopped in a low state for reduced EMI when  
the lines are not needed.  
Block Diagram  
Pin Configuration  
28-Pin SSOP & TSSOP  
0258K 12/15/08  
PentiumPro is a trademark of Intel Corporation  
I2C is a trademark of Philips Corporation  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the latest  
version of all device data to verify that any information being relied upon by the  
customer is current and accurate.  

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