87C196KR/KQ 87C196JV/JT 87C196JR/JQ
The MCS 96 microcontroller family members are all
high performance microcontrollers with a 16-bit
Up to 37 Interrupt Vectors
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Up to 512 Bytes of Code RAM
Up to 1.5 Kbytes of Register RAM
CPU. The 87C196Kx/Jx family members listed
above are composed of the high-speed (16 MHz)
core as well as the following peripherals: up to 48
Kbytes of Programmable EPROM, up to 1.5 Kbytes
of Register RAM, 512 bytes of code RAM (16-bit
addressing modes) with the ability to execute from
‘‘Windowing’’ Allows 8-Bit Addressing to Some
16-Bit Addresses
1.75 ms 16 x 16 Multiply
3 ms 32/16 Divide
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g
this RAM space, an eight channel-10-Bit/ 3 LSB
analog to digital converter with programmable S/H
Oscillator Fail Detect
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times with conversion times 5 ms at 16 MHz, an
asynchronous/synchronous serial I/O port (8096
compatible) with a dedicated 16-bit baud rate gener-
ator, an additional synchronous serial I/O port (8096
compatible) with a dedicated 16-bit baud rate gener-
ator, an additional synchronous serial I/O port with
full duplex master/slave transceivers, a flexible tim-
er/counter structure with prescaler, cascading, and
quadrature capabilities, 10 modularized multiplexed
high speed I/O for capture and compare (called
Event Processor Array) with 250 ns resolution and
double buffered inputs, a sophisticated prioritized in-
terrupt structure with programmable Peripheral
Transaction Server (PTS). The PTS has several
channel modes, including single/burst block trans-
fers from any memory location to any memory loca-
tion, a PWM and PWM toggle mode to be used in
conjunction with the EPA, and an A/D scan mode.
PERIPHERAL FEATURES
Programmable A/D Conversion and S/H Times
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10 Capture/Compare I/O with 2 Flexible Timers
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Synchronous Serial I/O Port for Full Duplex Seri-
al I/O
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Total Utilization of ALL Available Pins (I/O Mux’d
with Control)
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2 16-Bit Timers with Prescale, Cascading and
Quadrature Counting Capabilities
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Up to 12 Externally Triggered Interrupts
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NEW INSTRUCTIONS
XCH/XCHB
Additional SFR space is allocated for the EPA and
can be ‘‘windowed’’ into the lower Register RAM
area.
Exchange the contents of two locations, either Word
or Byte is supported.
Please refer to the following datasheets for higher
frequency versions of devices contained within this
BMOVi
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datasheet: 20 MHz 87C196JT: Order
20 MHz 87C196JV: Order Number 272580.
272529;
Interruptable Block Move Instruction, allows the user
to be interrupted during long executing Block Moves.
ARCHITECTURE
The 87C196KR/KQ/JV/JT/JR/JQ are members of
the MCS 96 microcontroller family, has the same ar-
chitecture and uses the same instruction set as the
80C196KB/KC. Many new features have been add-
ed including:
TIJMP
Table Indirect JUMP. This instruction incorporates a
way to do complex CASE level branches through
one instruction. An example of such code savings:
several interrupt sources and only one interrupt vec-
tor. The TIJMP instruction will sort through the
sources and branch to the appropriate sub-code lev-
el in one instruction. This instruction was added es-
pecially for the EPA structure, but has other code
saving advantages.
CPU FEATURES
Powerdown and Idle Modes
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16 MHz Operating Frequency
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A High Performance Peripheral Transaction Serv-
er (PTS)
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EPTS/DPTS
Enable and Disable PTS Interrupts (Works like EI
and DI).
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