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87C196KR PDF预览

87C196KR

更新时间: 2024-01-19 21:37:59
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
25页 326K
描述
ADVANCED 16-BIT CHMOS MICROCONTROLLER

87C196KR 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:68
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.83具有ADC:YES
地址总线宽度:16位大小:16
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:16
JESD-30 代码:S-PQCC-J68长度:24.2316 mm
I/O 线路数量:56端子数量:68
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
ROM可编程性:OTPROM座面最大高度:4.83 mm
速度:16 MHz最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:24.2316 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER

87C196KR 数据手册

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87C196KR/KQ 87C196JV/JT 87C196JR/JQ  
The MCS 96 microcontroller family members are all  
high performance microcontrollers with a 16-bit  
Up to 37 Interrupt Vectors  
#
#
#
#
Up to 512 Bytes of Code RAM  
Up to 1.5 Kbytes of Register RAM  
CPU. The 87C196Kx/Jx family members listed  
above are composed of the high-speed (16 MHz)  
core as well as the following peripherals: up to 48  
Kbytes of Programmable EPROM, up to 1.5 Kbytes  
of Register RAM, 512 bytes of code RAM (16-bit  
addressing modes) with the ability to execute from  
‘‘Windowing’’ Allows 8-Bit Addressing to Some  
16-Bit Addresses  
1.75 ms 16 x 16 Multiply  
3 ms 32/16 Divide  
#
#
#
g
this RAM space, an eight channel-10-Bit/ 3 LSB  
analog to digital converter with programmable S/H  
Oscillator Fail Detect  
k
times with conversion times 5 ms at 16 MHz, an  
asynchronous/synchronous serial I/O port (8096  
compatible) with a dedicated 16-bit baud rate gener-  
ator, an additional synchronous serial I/O port (8096  
compatible) with a dedicated 16-bit baud rate gener-  
ator, an additional synchronous serial I/O port with  
full duplex master/slave transceivers, a flexible tim-  
er/counter structure with prescaler, cascading, and  
quadrature capabilities, 10 modularized multiplexed  
high speed I/O for capture and compare (called  
Event Processor Array) with 250 ns resolution and  
double buffered inputs, a sophisticated prioritized in-  
terrupt structure with programmable Peripheral  
Transaction Server (PTS). The PTS has several  
channel modes, including single/burst block trans-  
fers from any memory location to any memory loca-  
tion, a PWM and PWM toggle mode to be used in  
conjunction with the EPA, and an A/D scan mode.  
PERIPHERAL FEATURES  
Programmable A/D Conversion and S/H Times  
#
10 Capture/Compare I/O with 2 Flexible Timers  
#
Synchronous Serial I/O Port for Full Duplex Seri-  
al I/O  
#
Total Utilization of ALL Available Pins (I/O Mux’d  
with Control)  
#
2 16-Bit Timers with Prescale, Cascading and  
Quadrature Counting Capabilities  
#
Up to 12 Externally Triggered Interrupts  
#
NEW INSTRUCTIONS  
XCH/XCHB  
Additional SFR space is allocated for the EPA and  
can be ‘‘windowed’’ into the lower Register RAM  
area.  
Exchange the contents of two locations, either Word  
or Byte is supported.  
Please refer to the following datasheets for higher  
frequency versions of devices contained within this  
BMOVi  
Ý
datasheet: 20 MHz 87C196JT: Order  
20 MHz 87C196JV: Order Number 272580.  
272529;  
Interruptable Block Move Instruction, allows the user  
to be interrupted during long executing Block Moves.  
ARCHITECTURE  
The 87C196KR/KQ/JV/JT/JR/JQ are members of  
the MCS 96 microcontroller family, has the same ar-  
chitecture and uses the same instruction set as the  
80C196KB/KC. Many new features have been add-  
ed including:  
TIJMP  
Table Indirect JUMP. This instruction incorporates a  
way to do complex CASE level branches through  
one instruction. An example of such code savings:  
several interrupt sources and only one interrupt vec-  
tor. The TIJMP instruction will sort through the  
sources and branch to the appropriate sub-code lev-  
el in one instruction. This instruction was added es-  
pecially for the EPA structure, but has other code  
saving advantages.  
CPU FEATURES  
Powerdown and Idle Modes  
#
16 MHz Operating Frequency  
#
A High Performance Peripheral Transaction Serv-  
er (PTS)  
#
EPTS/DPTS  
Enable and Disable PTS Interrupts (Works like EI  
and DI).  
2

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