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87421AMIT PDF预览

87421AMIT

更新时间: 2023-01-03 00:53:47
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
14页 255K
描述
Low Skew Clock Driver, PDSO8

87421AMIT 数据手册

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÷1/÷2 DIFFERENTIAL-TO-LVDS  
CLOCK GENERATOR  
ICS87421I  
GENERAL DESCRIPTION  
FEATURES  
The ICS87421I is a high performance ÷1/÷2  
• One differential LVDS output  
ICS  
Differential-to-LVDS Clock Generator and a mem-  
ber of the HiPerClockS™ family of High Perfor-  
mance Clock Solutions from IDT. The CLK, nCLK  
pair can accept most standard differential input  
• One differential CLK, nCLK input pair  
HiPerClockS™  
• CLK, nCLK pair can accept the following differential input  
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
levels. The ICS87421I is characterized to operate from a 3.3V  
power supply. Guaranteed part-to-part skew characteristics  
make the ICS87421I ideal for those clock distribution applica-  
tions demanding well defined performance and repeatability.  
• Maximum clock input frequency: 1GHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVDS levels with resistor bias on nCLK input  
• Part-to-part skew: 500ps (maximum)  
• Propagation delay: 1.7ns (maximum)  
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)  
• Full 3.3V operating supply  
• -40°C to 85°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK  
nCLK  
MR  
VDD  
Q
1
2
3
4
8
7
6
5
÷1  
÷2  
0
1
Q
nQ  
CLK  
nCLK  
nQ  
GND  
R
F_SEL  
ICS87421I  
MR  
8-Lead SOIC  
3.90mm x 4.90mm x 1.37mm package body  
M Package  
Top View  
F_SEL  
IDT/ ICSLVDS CLOCK GENERATOR  
1
ICS87421AMI REV. A OCTOBER 3, 2007  

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