874005AG-04LF

更新时间： 2024-01-13 14:57:15

品牌	Logo	应用领域
艾迪悌 - IDT		衰减器 PC
页数	文件大小	规格书
13页	274K
描述
PCI EXPRESS™ JITTER ATTENUATOR

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874005AG-04LF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP-24	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	7.63
Is Samacsys：	N	系列：	874005
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	7.8 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	1
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	5
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
最小 fmax：	98 MHz	Base Number Matches：	1

874005AG-04LF 数据手册

ICS874005-04

PCI EXPRESS™ JITTER ATTENUATOR

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The

ICS874005-04 provides separate power supplies to isolate

any high switching noise from the outputs to the internal PLL.

V_DD, V_DDAand V_DDOshould be individually connected to the

power supply plane through vias, and 0.01µF bypass

capacitors should be used for each pin. Figure 1 illustrates

this for a generic V_DDpin and also shows that V_DDArequires

that an additional10Ω resistor along with a 10µF bypass

capacitor be connected to the V_DDApin.

3.3V

V_DD

.01μF

10Ω

V_DDA

10μF

FIGURE 1. POWER SUPPLY FILTERING

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

LVCMOS CONTROL PINS

LVDS OUTPUTS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, we

recommend that there is no trace attached.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V /2 is

generated by the bias resistors R1, R2 and C1. This bias ^Dc^Dircuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

CLK

nCLK

0.1u

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

IDT^™/ ICS^™PCI EXPRESS™ JITTER ATTENUATOR

ICS874005AG-04 REV. A JULY 29, 2008

1...4 5 678 9 10...13

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与874005AG-04LF相关器件

型号	品牌	描述	获取价格	数据表
874005AG-04LFT	IDT	PCI EXPRESS™ JITTER ATTENUATOR	获取价格
874005AGT	IDT	PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.4	获取价格
8740060U1000	ETC	22 AWG solid tinned copper conductors, PVC insulation,	获取价格
8740060U500	ETC	22 AWG solid tinned copper conductors, PVC insulation,	获取价格
87401-105LF	AMPHENOL	Board Connector, 10 Contact(s), 2 Row(s), Male, Straight, Surface Mount Terminal, LEAD FRE	获取价格
87401-110	AMPHENOL	Board Connector, 20 Contact(s), 2 Row(s), Male, Straight, 0.05 inch Pitch, Surface Mount T	获取价格

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