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8634BY-01LF PDF预览

8634BY-01LF

更新时间: 2024-02-13 21:48:38
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 284K
描述
TQFP-32, Tray

8634BY-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:8.62
系列:8634输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.2 ns传播延迟(tpd):4.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mm最小 fmax:700 MHz
Base Number Matches:1

8634BY-01LF 数据手册

 浏览型号8634BY-01LF的Datasheet PDF文件第3页浏览型号8634BY-01LF的Datasheet PDF文件第4页浏览型号8634BY-01LF的Datasheet PDF文件第5页浏览型号8634BY-01LF的Datasheet PDF文件第7页浏览型号8634BY-01LF的Datasheet PDF文件第8页浏览型号8634BY-01LF的Datasheet PDF文件第9页 
ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
APPLICATION INFORMATION  
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS  
Figure 1 shows how the differential input can be wired to accept  
single ended levels. The reference voltage V_REF ~ VCC/2 is  
generated by the bias resistors R1, R2 and C1.This bias circuit  
should be located as close as possible to the input pin.The ratio  
of R1 and R2 might need to be adjusted to position the V_REF  
in the center of the input voltage swing.For example, if the input  
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V  
and R2/R1 = 0.609.  
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT  
TERMINATION FOR LVPECL OUTPUTS  
The clock layout topology shown below is a typical termination  
for LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
should be used to maximize operating frequency and minimize  
signal distortion. Figures 2A and 2B show two different layouts  
which are recommended only as guidelines.Other suitable clock  
layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed  
circuit and clock component process variations.  
FOUT and nFOUT are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, termi-  
nating resistors (DC current path to ground) or current sources  
must be used for functionality. These outputs are designed to  
drive 50Ω transmission lines. Matched impedance techniques  
FIGURE 2A. LVPECL OUTPUT TERMINATION  
FIGURE 2B. LVPECL OUTPUT TERMINATION  
8634BY-01  
www.idt.com  
REV. D MAY 12, 2014  
6

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