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8633AF-01 PDF预览

8633AF-01

更新时间: 2024-01-05 16:03:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 291K
描述
PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X 10.20 MM, 1.75 MM HEIGHT, MO-150, SSOP-28

8633AF-01 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.7
系列:8633输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:3最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:4.9 ns传播延迟(tpd):4.9 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:2 mm子类别:Clock Driver
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mmBase Number Matches:1

8633AF-01 数据手册

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ICS8633-01  
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
VCCO - 1.4  
VCCO - 2.0  
0.6  
Typical  
Maximum  
VCCO - 0.9  
VCCO - 1.7  
1.0  
Units  
VOH  
Output High Voltage; NOTE 1  
V
V
V
VOL  
Output Low Voltage; NOTE 1  
VSWING  
Peak-to-Peak Output Voltage Swing  
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.  
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
fIN Input Frequency  
Test Conditions  
PLL_SEL = 1  
PLL_SEL = 0  
Minimum Typical Maximum Units  
31.25  
700  
700  
MHz  
MHz  
CLK0, nCLK0,  
CLK1, nCLK1  
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
fMAX Output Frequency  
tPD  
Test Conditions  
Minimum Typical Maximum Units  
700  
4.9  
MHz  
ns  
Propagation Delay; NOTE 1  
PLL_SEL = 0V, ƒ700MHz  
2.8  
-50  
PLL Reference Zero Delay;  
NOTE 2, 4  
t(Ø)  
PLL_SEL = 3.3V  
50  
150  
ps  
tsk(o)  
tjit(cc)  
tjit(θ)  
tL  
Output Skew; NOTE 3, 4  
Cycle-to-Cycle Jitter; NOTE 4, 6  
Phase Jitter; NOTE 4, 5, 6  
PLL Lock Time  
25  
25  
50  
1
ps  
ps  
ps  
ms  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20ꢀ to 80ꢀ @ 50MHz  
300  
47  
700  
53  
All parameters measured at fMAX unless noted otherwise.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal  
when the PLL is locked and the input reference frequency is stable.  
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 5: Phase jitter is dependent on the input source used.  
NOTE 6: Characterized at VCO frequency of 622MHz.  
8633AF-01  
www.idt.com  
REV. B AUGUST 2, 2010  
4

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