Datasheet > 85C51SND3BX03

85C51SND3BX03

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
爱特美尔 - ATMEL		解码器编码器
页数	文件大小	规格书
263页	3620K
描述
Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface

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数据手册

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85C51SND3BX03 数据手册

AT85C51SND3Bx

Signals Description

System

Table 1. System Signal Description

Signal

Name

Alternate

Function

Type Description

Reset Input

Holding this pin low for 64 oscillator periods while the oscillator is

running resets the device. The Port pins are driven to their reset

conditions when a voltage lower than V_ILis applied, whether or not the

oscillator is running.

This pin has an internal pull-up resistor (R_RST) which allows the device

RST

I/O

to be reset by connecting a capacitor between this pin and V_SS

Asserting RST when the chip is in Idle mode or Power-Down mode

returns the chip to normal operation.

In order to reset external components connected to the RST line a low

level 96-clock period pulse is generated when the watchdog timer

reaches its time-out period.

In System Programming

ISP

Assert this pin during reset phase to enter the in system programming

mode.

OCDT

Table 2. Ports Signal Description

Signal

Name

Alternate

Function

Type Description

Port 0

P0.7:0

I/O

LD7:0

P0 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 1

P1.7:0

P2.7:0

I/O

KIN3:0

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

SDINS

SDLCK

SDCMD

SDCLK

Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

SDDAT3:0

RXD

MISO

TXD

MOSI

INT0

RTS

SCK

P3.4:0

P3.7:6

Port 3

I/O

P3 is a 7-bit bidirectional I/O port with internal pull-ups.

INT1

CTS

UVCON

UID

7632A–MP3–03/06

1...4 5 678 9 10...263

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