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8530DY-01T PDF预览

8530DY-01T

更新时间: 2024-02-03 05:53:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 178K
描述
Clock Driver, PQFP48

8530DY-01T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
湿度敏感等级:3端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
Prop。Delay @ Nom-Sup:2 ns认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

8530DY-01T 数据手册

 浏览型号8530DY-01T的Datasheet PDF文件第2页浏览型号8530DY-01T的Datasheet PDF文件第3页浏览型号8530DY-01T的Datasheet PDF文件第4页浏览型号8530DY-01T的Datasheet PDF文件第5页浏览型号8530DY-01T的Datasheet PDF文件第6页浏览型号8530DY-01T的Datasheet PDF文件第7页 
ICS8530-01  
LOW SKEW, 1-TO-16  
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8530-01 is a low skew, 1-to-16 Differen- Sixteen differential 3.3V LVPECL outputs  
ICS  
HiPerClockS™  
tial-to-3.3V LVPECL Fanout Buffer and a mem-  
CLK, nCLK input pair  
ber of the HiPerClockS™family of High Perfor-  
mance Clock Solutions from ICS.The CLK, nCLK  
pair can accept most standard differential input  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
levels. The high gain differential amplifier accepts peak-to-  
peak input voltages as small as 150mV as long as the com-  
mon mode voltage is within the specified minimum and maxi-  
mum range.  
Maximum output frequency: 500MHz  
Translates any single-ended input signal to  
3.3V LVPECL levels with a resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics make  
the ICS8530-01 ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
Output skew: 75ps (maximum)  
Part-to-part skew: 250ps (maximum)  
Additive phase jitter, RMS: 0.03ps (typical)  
3.3V output operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK  
nCLK  
48 47 46 45 44 43 42 41 40 39 38 37  
Q0  
Q15  
CLK  
VCCO  
nQ0  
Q0  
VCCO  
Q11  
nQ11  
Q10  
nQ10  
VEE  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
nQ0  
nQ15  
2
Q1  
nQ1  
Q14  
nQ14  
3
4
nQ1  
Q1  
5
Q2  
nQ2  
Q13  
nQ13  
6
ICS8530-01  
VEE  
Q9  
7
Q3  
nQ3  
Q12  
nQ12  
nQ2  
Q2  
nQ9  
Q8  
8
9
Q4  
nQ4  
Q11  
nQ11  
nQ3  
Q3  
nQ8  
VCCO  
VCC  
10  
11  
12  
Q5  
nQ5  
Q10  
nQ10  
Vcco  
13 14 15 16 17 18 19 20 21 22 23 24  
Q6  
nQ6  
Q9  
nQ9  
Q7  
nQ7  
Q8  
nQ8  
48-Pin LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8530DY-01  
www.icst.com/products/hiperclocks.html  
REV.E MAY 19, 2006  
1

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