Datasheet > 84329AVLFT

84329AVLFT

更新时间： 2023-02-26 14:41:02

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	279K
描述
Clock Generator, PQCC28

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84329AVLFT 数据手册

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE

Inputs

Conditions

nP_LOAD

S_LOAD S_CLOCK S_DATA

Reset. M and N bits are all set HIGH.

Data on M and N inputs passed directly to M divider and

N output divider. TEST mode 000.

↑

Data Data

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

Contents of the shift register are passed to the M divider

and N output divider.

↑

Data

↓

Data

M divide and N output divide values are latched.

Parallel or serial input do not affect shift registers.

NOTE: L = LOW

H = HIGH

X = Don't care

↑ = Rising edge transition

↓= Falling edge transition

TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

256

128

VCO Frequency

(MHz)

M Divide

200

201

202

203

•

200

201

202

203

•

509

510

511

509

510

511

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.

TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

Inputs

Output Frequency (MHz)

N Divider Value

Minimum

200

Maximum

700

100

350

175

87.5

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

1 2 345 6 7...19

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