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84329AVLFT PDF预览

84329AVLFT

更新时间: 2023-02-26 14:41:02
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
19页 279K
描述
Clock Generator, PQCC28

84329AVLFT 数据手册

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ICS84329  
Integrated  
Circuit  
Systems, Inc.  
700MH  
Z
, LOW  
J
ITTER, CRYSTAL  
-TO-3.3V  
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER  
S
TABLE 1. PIN DESCRIPTIONS  
Name  
Type  
Description  
VCCA  
Power  
Analog supply pin.  
XTAL_IN,  
XTAL_OUT  
Input  
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.  
Output enable. When logic HIGH, the outputs are enabled (default).  
When logic LOW, the outputs are disabled and drive differential low:  
FOUT = LOW, nFOUT = HIGH. LVCMOS / LVTTL interface levels.  
Parallel load input. Determines when data present at M8:M0 is loaded into  
M divider, and when data present at N1:N0 sets the N output divide value.  
LVCMOS / LVTTL interface levels.  
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.  
LVCMOS / LVTTL interface levels.  
Determines N output divider value as defined in Table 3C Function Table.  
LVCMOS / LVTTL interface levels.  
OE  
Input  
Pullup  
nP_LOAD  
Input  
Input  
Pullup  
M0, M1, M2, M3,  
M4, M5, M6, M7, M8  
Pullup  
Pullup  
N0, N1  
VEE  
Input  
Power  
Output  
Negative supply pins.  
Test output which is used in the serial mode of operation.  
LVCMOS / LVTTL interface levels.  
TEST  
VCC  
Power  
Output  
Core supply pins.  
nFOUT, FOUT  
Differential output for the synthesizer. 3.3V LVPECL interface levels.  
Clocks the serial data present at S_DATA input into the shift register on the  
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.  
Shift register serial input. Data sampled on the rising edge of S_CLOCK.  
LVCMOS / LVTTL interface levels.  
Controls transition of data from shift register into the M divider.  
LVCMOS / LVTTL interface levels.  
S_CLOCK  
S_DATA  
Input  
Input  
Input  
Pulldown  
Pulldown  
Pulldown  
S_LOAD  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Input Capacitance  
Input Pullup Resistor  
4
pF  
KΩ  
KΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
84329AV  
www.icst.com/products/hiperclocks.html  
REV. D DECEMBER 15, 2004  
3

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