Datasheet > 843201-375

843201-375

更新时间： 2024-02-13 20:21:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	267K
描述
FemtoClockÂ® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer

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中文翻译

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数据手册

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843201-375 数据手册

FemtoClock^®Crystal-to-LVPECL 375MHz

Frequency Margining Synthesizer

843201-375

DATASHEET

GENERAL DESCRIPTION

FEATURES

• One 375MHz nominal LVPECL output

The 843201-375 is a low phase-noise frequency margining

synthesizer. In the default mode, the device nominally generates a

375MHz LVPECL output clock signal from a 25MHz crystal input.

There is also a frequency margining mode available where the

device can be conﬁgured, using control pins, to vary the output

frequency up or down from nominal by 5%. The 843201-375 is

provided in a 16-pin TSSOP package.

• Crystal oscillator interface designed for 25MHz, 18pF parallel

resonant crystal

• Output frequency can be varied 5% from nominal

• VCO range: 700MHz - 800MHz

• RMS phase jitter @ 375MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.72ps (typical) @ 3.3V

• Output supply modes

Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• Functional replacement part 8T49N241-dddNLGI

PIN ASSIGNMENT

BLOCK DIAGRAM

Pulldown

V_CC

MODE

nPLL_SEL

V_CCO

V_CC

XTAL_IN

XTAL_OUT

MARGIN

V_EE

25MHz

XTAL_IN

Predivider

Phase

Detector

VCO

nPLL_SEL

÷2

OSC

700 - 800MHz

XTAL_OUT

843201-375

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm

package body

÷30

(÷57, ÷63)

G Package

Top View

Pulldown

MODE

MARGIN

843201-375 REVISION A 8/21/15

12 3 4 5 6 7...19

中文翻译

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