Datasheet > 842023AGLF

842023AGLF

更新时间： 2024-02-09 17:04:42

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
12页	757K
描述
Clock Generator, PDSO8

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技术参数
数据手册

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842023AGLF 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.84
JESD-30 代码：	R-PDSO-G8	端子数量：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	2.5/3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	84 mA	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

842023AGLF 数据手册

ICS842023

FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR

PRELIMINARY

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perform-

ance, power supply isolation is required. The ICS842023 provides

separate power supplies to isolate any high switching noise from

the outputs to the internal PLL. V_DDand V_DDAshould be

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 3

illustrates this for a generic V_DDpin and also shows that V_DDA

requires that an additional 10Ω resistor along with a 10µF bypass

capacitor be connected to the V_DDApin.

3.3V or 2.5V

V_DD

.01µF

10Ω

V_DDA

.01µF

10µF

Figure 3. Power Supply Filtering

Schematic Example

Figure 4 shows an example of the ICS842023 application

schematic. In this example, the device is operated at V_DD= 3.3V.

The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF

and C2 = 22pF are recommended for frequency accuracy. For

different board layouts, the C1 and C2 may be slightly adjusted for

optimizing frequency accuracy. An example of HSTL termination is

shown in this schematic.

VDD

VDDA

0.1u

10u

0.1uF

Zo = 50 Ohm

VDDA

VDD

GND

XTAL_OUT

XTAL_IN

25MHz

18pF

22pF

Zo = 50 Ohm

ICS842023

VDD=3.3V

22pF

Logic Control Input Examples

Set Logic

Input to

'1'

Set Logic

VDD

Input to

'0'

RU1

RU2

Not Install

To Logic

Input

To Logic

Input

pins

RD1

RD2

Not Install

Figure 4. ICS842023 Schematic Example

IDT™ / ICS™ HSTL CLOCK GENERATOR

ICS842023AG REV. B JULY 15, 2008

1...4 5 678 9 10...12

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