ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
XTAL_IN,
XTAL_OUT
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z).
When logic LOW, the internal dividers and the outputs are enabled.
Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C.
1, 2
Input
Input
3
MR/nOE
Pulldown
4, 14,
24, 31
VDD
Power
Core supply pins.
5, 6
7, 8
Q0, nQ0
Q1, nQ1
GND
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
9, 19, 32
10, 11
12, 13
15, 16
17, 18
20, 21
22, 23
25
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
(475Ω) from this pin to ground provides a reference current used for
differential current-mode Qx/nQx clock outputs.
26
IREF
Output
Selects PLL operation/PLL bypass operation. Asynchronous function.
LVCMOS/LVTTL interface levels. See Table 3B.
27
28
29
30
BYPASS
VDDA
Input
Power
Input
Input
Pulldown
Analog supply pin.
Reference select. Selects the input reference source. See Table 3D.
LVCMOS/LVTTL interface levels.
REF_SEL
REF_IN
Pulldown
Pulldown LVCMOS/LVTTL PLL reference clock input.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
TABLE 3A. FSEL FUNCTION TABLE (fREF = 25MHZ)
TABLE 3B. BYPASS FUNCTION TABLE
Input
Input
Outputs
FSEL
N
5
4
Q0:7/nQ0:7
BYPASS
PLL Configuration
0
1
VCO/5 (100MHz) PCIe (default)
VCO/4 (125MHz) sRIO
0
1
PLL enabled (default)
PLL bypassed (fOUT = fREF ÷ N)
TABLE 3C. MR/nOE FUNCTION TABLE
Input
TABLE 3D. REF_SEL FUNCTION TABLE
Input
REF_SEL
Input Reference
XTAL (default)
REF_IN
MR/nOE Function
0
1
0
1
Outputs enabled (default)
Device reset, outputs disabled (high-impedance)
IDT™ / ICS™ HCSL CLOCK GENERATOR
2
ICS841608AKI REV. A JUNE 18, 2008