Datasheet > 8302101SA

8302101SA

更新时间： 2024-01-12 11:50:49

品牌	Logo	应用领域
德州仪器 - TI		输出元件逻辑集成电路触发器
页数	文件大小	规格书
7页	121K
描述
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

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8302101SA 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.44	其他特性：	PARALLEL OUTPUT IS LATCHED; UNLATCHED SERIAL SHIFT RIGHT OUTPUT
计数方向：	RIGHT	系列：	4000/14000/40000
逻辑集成电路类型：	SERIAL IN PARALLEL OUT	位数：	8
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	CERAMIC, GLASS-SEALED	封装形式：	IN-LINE
认证状态：	Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	18 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	5 V	技术：	CMOS
温度等级：	MILITARY	端子节距：	2.54 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	7.62 mm	Base Number Matches：	1

8302101SA 数据手册

SN54ALS299, SN74ALS299

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH 3-STATE OUTPUTS

SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994

SN54ALS299 . . . J PACKAGE

SN74ALS299 . . . DW OR N PACKAGE

(TOP VIEW)

• Multiplexed I/O Ports Provide Improved Bit

Density

• Four Modes of Operation:

– Hold (Store)

OE1

OE2

– Shift Right

– Shift Left

– Load Data

G/Q

H′

• Operate With Outputs Enabled or at High

E/Q

H/Q

Impedance

C/Q

F/Q

• 3-State Outputs Drive Bus Lines Directly

• Can Be Cascaded for n-Bit Word Lengths

• Direct Overriding Clear

A/Q

D/Q

B/Q

A′

CLR

GND

CLK

• Applications:

– Stacked or Push-Down Registers

– Buffer Storage

SN54ALS299 . . . FK PACKAGE

(TOP VIEW)

– Accumulator Registers

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

20 19

G/Q

E/Q

H′

description

C/Q

A/Q

H/Q

F/Q

These 8-bit universal shift/storage registers

feature multiplexed I/O ports to achieve full 8-bit

data handling in a single 20-pin package. Two

function-select (S0, S1) inputs and two output-

enable (OE1, OE2) inputs can be used to choose

the modes of operation listed in the function table.

D/Q

A′

9 10 11 12 13

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs

in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading

out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs

asynchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs, but has

no effect on clearing, shifting, or storing data.

The SN54ALS299 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ALS299 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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