IDT82V3202
EBU WAN PLL
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32
3.10.1.5.4 Manual ........................................................................................................................................................... 32
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32
3.11 DPLL OUTPUT .............................................................................................................................................................................................. 34
3.11.1 PFD Output Limit ............................................................................................................................................................................ 34
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34
3.11.3 PBO ................................................................................................................................................................................................. 34
3.11.4 Four Paths of T0 DPLL Outputs .................................................................................................................................................... 34
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 36
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 36
3.13.1 Output Clocks ................................................................................................................................................................................. 36
3.13.2 Frame SYNC Output Signal ........................................................................................................................................................... 38
3.14 INTERRUPT SUMMARY ............................................................................................................................................................................... 40
3.15 T0 SUMMARY ............................................................................................................................................................................................... 40
3.16 LINE CARD APPLICATION .......................................................................................................................................................................... 41
4 I2C PROGRAMMING INTERFACE .................................................................................................................................. 42
4.1 FUNCTION DESCRIPTION ........................................................................................................................................................................... 42
4.1.1 Data Transfer Format ..................................................................................................................................................................... 43
4.1.1.1 Slave-receiver Mode (Write) ............................................................................................................................................. 43
4.1.1.2 Slave-transmitter Mode (Read) ........................................................................................................................................ 43
4.1.2 Address Assignment ..................................................................................................................................................................... 44
4.2 TIMING DEFINITION ..................................................................................................................................................................................... 44
5 JTAG ................................................................................................................................................................................ 46
6 PROGRAMMING INFORMATION .................................................................................................................................... 47
6.1 REGISTER MAP ............................................................................................................................................................................................ 47
6.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 51
6.2.1 Global Control Registers ............................................................................................................................................................... 51
6.2.2 Interrupt Registers ......................................................................................................................................................................... 58
6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 62
6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 67
6.2.5 T0 DPLL Input Clock Selection Registers .................................................................................................................................... 75
6.2.6 T0 DPLL State Machine Control Registers .................................................................................................................................. 77
6.2.7 T0 DPLL & T0/T4 APLL Configuration Registers ........................................................................................................................ 79
6.2.8 Output Configuration Registers .................................................................................................................................................... 90
6.2.9 PBO & Phase Offset Control Registers ........................................................................................................................................ 93
6.2.10 Synchronization Configuration Registers ................................................................................................................................... 94
7 THERMAL MANAGEMENT ............................................................................................................................................. 95
7.1 JUNCTION TEMPERATURE ........................................................................................................................................................................ 95
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ..................................................................................................................... 95
7.3 HEATSINK EVALUATION ............................................................................................................................................................................ 95
7.4 VFQFPN EPAD THERMAL RELEASE PATH .............................................................................................................................................. 96
8 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 97
8.1 ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 97
8.2 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 97
8.3 I/O SPECIFICATIONS ................................................................................................................................................................................... 98
8.3.1 CMOS Input / Output Port .............................................................................................................................................................. 98
8.3.2 PECL / LVDS Output Port ............................................................................................................................................................ 100
8.3.2.1 PECL Output Port ........................................................................................................................................................... 100
8.3.2.2 LVDS Output Port ........................................................................................................................................................... 101
8.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 102
Table of Contents
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September 11, 2009
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