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82V3202NLG8 PDF预览

82V3202NLG8

更新时间: 2024-02-24 06:55:43
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
117页 1222K
描述
Telecom Circuit, 1-Func, PQCC68, GREEN, PLASTIC, VFQFPN-68

82V3202NLG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:GREEN, PLASTIC, VFQFPN-68
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.83
JESD-30 代码:S-PQCC-N68JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:68
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

82V3202NLG8 数据手册

 浏览型号82V3202NLG8的Datasheet PDF文件第1页浏览型号82V3202NLG8的Datasheet PDF文件第2页浏览型号82V3202NLG8的Datasheet PDF文件第4页浏览型号82V3202NLG8的Datasheet PDF文件第5页浏览型号82V3202NLG8的Datasheet PDF文件第6页浏览型号82V3202NLG8的Datasheet PDF文件第7页 
Table of Contents  
FEATURES.............................................................................................................................................................................. 9  
HIGHLIGHTS.................................................................................................................................................................................................... 9  
MAIN FEATURES ............................................................................................................................................................................................ 9  
OTHER FEATURES......................................................................................................................................................................................... 9  
APPLICATIONS....................................................................................................................................................................... 9  
DESCRIPTION....................................................................................................................................................................... 10  
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 11  
1 PIN ASSIGNMENT ........................................................................................................................................................... 12  
2 PIN DESCRIPTION .......................................................................................................................................................... 14  
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18  
3.1 RESET ........................................................................................................................................................................................................... 18  
3.2 MASTER CLOCK .......................................................................................................................................................................................... 18  
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 19  
3.3.1 Input Clocks .................................................................................................................................................................................... 19  
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19  
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20  
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21  
3.5.1 Activity Monitoring ......................................................................................................................................................................... 21  
3.5.2 Frequency Monitoring ................................................................................................................................................................... 22  
3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 23  
3.6.1 External Fast Selection .................................................................................................................................................................. 23  
3.6.2 Forced Selection ............................................................................................................................................................................ 24  
3.6.3 Automatic Selection ....................................................................................................................................................................... 24  
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25  
3.7.1 DPLL Locking Detection ................................................................................................................................................................ 25  
3.7.1.1 Fast Loss .......................................................................................................................................................................... 25  
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25  
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25  
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25  
3.7.2 Locking Status ............................................................................................................................................................................... 25  
3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 25  
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27  
3.8.1 Input Clock Validity ........................................................................................................................................................................ 27  
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27  
3.8.2.1 Revertive Switch ............................................................................................................................................................... 27  
3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 27  
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 27  
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29  
3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 31  
3.10.1 Six Operating Modes ..................................................................................................................................................................... 31  
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 31  
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 31  
3.10.1.3 Locked Mode .................................................................................................................................................................... 31  
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 31  
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31  
3.10.1.5 Holdover Mode ................................................................................................................................................................. 31  
Table of Contents  
3
September 11, 2009  

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