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82C37

更新时间： 2024-02-12 07:18:56
品牌 Logo 应用领域
哈里斯 - HARRIS 控制器
页数 文件大小 规格书
23页 207K
描述
CMOS High Performance Programmable DMA Controller

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S E M I C O N D U C T O R  
82C37A  
CMOS High Performance  
Programmable DMA Controller  
March 1997  
Features  
Description  
• Compatible with the NMOS 8237A  
The 82C37A is an enhanced version of the industry standard  
8237A Direct Memory Access (DMA) controller, fabricated  
using Harris’ advanced 2 micron CMOS process. Pin  
compatible with NMOS designs, the 82C37A offers  
increased functionality, improved performance, and  
dramatically reduced power consumption. The fully static  
design permits gated clock operation for even further  
reduction of power.  
• Four Independent Maskable Channels with Autoinitial-  
ization Capability  
• Cascadable to any Number of Channels  
• High Speed Data Transfers:  
- Up to 4MBytes/sec with 8MHz Clock  
- Up to 6.25MBytes/sec with 12.5MHz Clock  
The 82C37A controller can improve system performance by  
allowing external devices to transfer data directly to or from  
system memory. Memory-to-memory transfer capability is  
also provided, along with a memory block initialization fea-  
ture. DMA requests may be generated by either hardware or  
software, and each channel is independently programmable  
with a variety of features for flexible operation.  
• Memory-to-Memory Transfers  
• Static CMOS Design Permits Low Power Operation  
- ICCSB = 10µA Maximum  
- ICCOP = 2mA/MHz Maximum  
• Fully TTL/CMOS Compatible  
The 82C37A is designed to be used with an external  
address latch, such as the 82C82, to demultiplex the most  
significant 8-bits of address. The 82C37A can be used with  
industry standard microprocessors such as 80C286, 80286,  
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and  
others. Multimode programmability allows the user to select  
from three basic types of DMA services, and reconfiguration  
under program control is possible even with the clock to the  
controller stopped. Each channel has a full 64K address and  
word count range, and may be programmed to autoinitialize  
these registers following DMA termination (end of process).  
• Internal Registers may be Read from Software  
Ordering Information  
PART NUMBER  
TEMPERATURE  
5MHz  
CP82C37A-5  
8MHz  
CP82C37A  
12.5MHz  
CP82C37A-12  
IP82C37A-12  
PACKAGE  
40 Ld PDIP  
RANGE  
PKG. NO.  
E40.6  
o
o
0 C to +70 C  
o
o
IP82C37A-5  
IP82C37A  
-40 C to +85 C  
E40.6  
o
o
CS82C37A-5  
CS82C37A  
CS82C37A-12  
IS82C37A-12  
44 Ld PLCC  
0 C to +70 C  
N44.65  
N44.65  
F40.6  
o
o
IS82C37A-5  
IS82C37A  
-40 C to +85 C  
o
o
CD82C37A-5  
CD82C37A  
CD82C37A-12  
ID82C37A-12  
40 Ld CERDIP  
0 C to +70 C  
o
o
ID82C37A-5  
ID82C37A  
-40 C to +85 C  
F40.6  
o
o
MD82C37A-5/B  
5962-9054301MQA  
MR82C37A-5/B  
5962-9054301MXA  
MD82C37A/B  
5962-9054302MQA  
MR82C37A/B  
5962-9054302MXA  
MD82C37A-12/B  
5962-9054303MQA  
MR82C37A-12/B  
5962-9054303MXA  
-55 C to +125 C  
F40.6  
SMD#  
F40.6  
o
o
44 Pad CLCC  
SMD#  
-55 C to +125 C  
J44.A  
J44.A  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 2967.1  
Copyright © Harris Corporation 1997  
4-192  
1234567...23

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