Datasheet > 80C52-12D

80C52-12D

更新时间： 2024-01-15 17:01:05

品牌	Logo	应用领域
TEMIC		微控制器
页数	文件大小	规格书
20页	227K
描述
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller

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技术参数
数据手册

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80C52-12D 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.78
Is Samacsys：	N	具有ADC：	NO
地址总线宽度：	16	位大小：	8
最大时钟频率：	12 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：	8
JESD-30 代码：	S-CQCC-J44	JESD-609代码：	e3
长度：	16.4465 mm	I/O 线路数量：	32
端子数量：	44	最高工作温度：	125 °C
最低工作温度：	-55 °C	PWM 通道：	NO
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	ROM可编程性：	MROM
座面最大高度：	4.83 mm	速度：	12 MHz
最大压摆率：	35 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	16.4465 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

80C52-12D 数据手册

MATRA MHS

80C32/80C52

1 FFFH). When EA is held low, the CPU executes only out

of external Program Memory. EA must not be floated.

PSEN

Program Store Enable output is the read strobe to external

Program Memory. PSEN is activated twice each machine

cycle during fetches from external Program Memory.

(However, when executing out of external Program

Memory, two activations of PSEN are skipped during

each access to external Data Memory). PSEN is not

activated during fetches from internal Program Memory.

PSEN can sink/source 8 LS TTL inputs. It can drive

CMOS inputs without an external pullup.

XTAL1

Input to the inverting amplifier that forms the oscillator.

Receives the external oscillator signal when an external

oscillator is used.

XTAL2

Output of the inverting amplifier that forms the oscillator.

This pin should be floated when an external oscillator is

used.

When EA is held high, the CPU executes out of internal

Program Memory (unless the Program Counter exceeds

Idle And Power Down Operation

Figure 3 shows the internal Idle and Power Down clock

configuration. As illustrated, Power Down operation

stops the oscillator. Idle mode operation allows the

interrupt, serial port, and timer blocks to continue to

function, while the clock to the CPU is gated off.

Symbol

Position

Name and Function

SMOD

PCON.7

Double Baud rate bit. When set to

a 1, the baud rate is doubled when

the serial port is being used in

either modes 1, 2 or 3.

(Reserved)

–

GF1

GF0

PCON.6

PCON.5

PCON.4

PCON.3

PCON.2

PCON.1

These special modes are activated by software via the

Special Function Register, PCON. Its hardware address is

87H. PCON is not bit addressable.

(Reserved)

General-purpose flag bit.

Power Down bit. Setting this bit

activates power down operation.

Idle mode bit. Setting this bit

activates idle mode operation.

Figure 3. Idle and Power Down Hardware.

IDL

PCON.0

If 1’s are written to PD and IDL at the same time. PD

takes, precedence. The reset value of PCON is

(000X0000).

Idle Mode

The instruction that sets PCON.0 is the last instruction

executed before the Idle mode is activated. Once in the

Idle mode the CPU status is preserved in its entirety : the

Stack Pointer, Program Counter, Program Status Word,

Accumulator, RAM and all other registers maintain their

data during idle. Table 1 describes the status of the

external pins during Idle mode.

PCON : Power Control Register

(MSB)

SMOD

(LSB)

IDL

–

GF1

GF0

Rev. E (31/08/95)

1 2 3 456 7 8...20

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80C52-16D	TEMIC	CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller	获取价格
80C52-16R	TEMIC	CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller	获取价格

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