Datasheet > 80C52-12

80C52-12

更新时间： 2024-01-15 08:57:41

品牌	Logo	应用领域
TEMIC		/
页数	文件大小	规格书
20页	221K
描述
CMOS 0 to 44 MHz Single Chip 8?bit Microntroller

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技术参数
数据手册

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80C52-12 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.78
Is Samacsys：	N	具有ADC：	NO
地址总线宽度：	16	位大小：	8
最大时钟频率：	12 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：	8
JESD-30 代码：	S-CQCC-J44	JESD-609代码：	e3
长度：	16.4465 mm	I/O 线路数量：	32
端子数量：	44	最高工作温度：	125 °C
最低工作温度：	-55 °C	PWM 通道：	NO
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	ROM可编程性：	MROM
座面最大高度：	4.83 mm	速度：	12 MHz
最大压摆率：	35 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	16.4465 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

80C52-12 数据手册

80C32/80C52

There are three ways to terminate the Idle mode.

Activation of any enabled interrupt will cause PCON.0 to

be cleared by hardware, terminating Idle mode. The

interrupt is serviced, and following RETI, the next

instruction to be executed will be the one following the

instruction that wrote 1 to PCON.0.

Power Down Mode

The instruction that sets PCON.1 is the last executed prior

to entering power down. Once in power down, the

oscillator is stopped. The contents of the onchip RAM and

the Special Function Register is saved during power down

mode. The hardware reset initiates the Special Fucntion

to minimize circuit power consumption. Care must be

taken to ensure the voltage is not reduced until the power

down mode is entered, and that the voltage is restored

before the hardware reset is applied which freezes the

oscillator. Reset should not be released until the oscillator

has restarted and stabilized.

The flag bits GF0 and GF1 may be used to determine

whether the interrupt was received during normal

execution or during the Idle mode. For example, the

instruction that writes to PCON.0 can also set or clear one

or both flag bits. When Idle mode is terminated by an

enabled interrupt, the service routine can examine the

status of the flag bits.

Table 1 describes the status of the external pins while in

The second way of terminating the Idle mode is with a

hardware reset. Since the oscillator is still running, the the power down mode. It should be noted that if the power

hardware reset needs to be active for only 2 machine down mode is activated while in external program

cycles (24 oscillator periods) to complete the reset memory, the port data that is held in the Special Function

pin is held high during the power down mode by the

strong pullup, T1, shown in Figure 4.

operation.

Table 1. Status of the external pins during idle and power down modes.

MODE

Idle

PROGRAM MEMORY

ALE

PSEN

PORT0

Port Data

Floating

Port Data

Floating

PORT1

Port Data

PORT2

Port Data

Address

PORT3

Port Data

Internal

External

Internal

External

Idle

Power Down

Port Data

Figure 4.I/O Buffers in the 80C52 (Ports 1, 2, 3).

Stop Clock Mode

Due to static design, the TEMIC 80C32/C52 clock speed

can be reduced until 0 MHz without any data loss in

memory or registers. This mode allows step by step

utilization, and permits to reduce system power

consumption by bringing the clock frequency down to

any value. At 0 MHz, the power consumption is the same

as in the Power Down Mode.

I/O Ports

The I/O buffers for Ports 1, 2 and 3 are implemented as

shown in figure 4.

MATRA MHS

Rev. G (14 Jan. 97)

1...3 4 567 8 9...20

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与80C52-12相关器件

型号	品牌	描述	获取价格	数据表
80C52-12/BMA	ETC	8-Bit Microcontroller	获取价格
80C52-12D	TEMIC	CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller	获取价格
80C52-12R	TEMIC	CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller	获取价格
80C52-16	TEMIC	CMOS 0 to 44 MHz Single Chip 8?bit Microntroller	获取价格
80C52-16/BMA	ETC	8-Bit Microcontroller	获取价格
80C52-16/BQA	ETC	8-Bit Microcontroller	获取价格

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