80C186EB/80C188EB, 80L186EB/80L188EB
A 12-bit address generator is maintained by the RCU
and is presented on the A12:1 address lines during
the refresh bus cycle. Address bits A19:13 are pro-
grammable to allow the refresh address block to be
located on any 8 Kbyte boundary.
Serial Communications Unit
The Serial Control Unit (SCU) of the 80C186EB con-
tains two independent channels. Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin). Each
channel has its own baud rate generator that is in-
dependent of the Timer/Counter Unit, and can be
internally or externally clocked at up to one half the
80C186EB operating frequency.
Power Management Unit
The 80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides three power modes: Ac-
tive, Idle, and Powerdown.
Independent baud rate generators are provided for
each of the serial channels. For the asynchronous
modes, the generator supplies an 8x baud clock to
both the receive and transmit register logic. A 1x
baud clock is provided in the synchronous mode.
Active Mode indicates that all units on the
80C186EB are functional and the device consumes
maximum power (depending on the level of periph-
eral operation). Idle Mode freezes the clocks of the
Execution and Bus units at a logic zero state (all
peripherals continue to operate normally).
Chip-Select Unit
The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
All internal registers hold their values provided V
is maintained. Current consumption is reduced to
just transistor junction leakage.
The 80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip-
selects to access both memories and peripherals. In
addition, each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically termi-
nate a bus cycle independent of the condition of the
READY input pin.
CC
80C187 Interface (80C186EB Only)
The 80C186EB (PLCC package only) supports the
direct connection of the 80C187 Numerics Coproc-
essor.
I/O Port Unit
The I/O Port Unit (IPU) on the 80C186EB supports
two 8-bit channels of input, output, or input/output
operation. Port 1 is multiplexed with the chip select
pins and is output only. Most of Port 2 is multiplexed
with the serial channel pins. Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EB has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’. The
ONCE mode is selected by forcing the A19/ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN is ac-
tive.
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed. A 9-bit
counter controls the number of clocks between re-
fresh requests.
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