Datasheet > 80C186EB13

80C186EB13

更新时间： 2022-11-26 03:03:03

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
59页	779K
描述
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

80C186EB13 数据手册

80C186EB/80C188EB, 80L186EB/80L188EB

5. SINT1 will only go active for one clock period

when a receive or transmit interrupt is pending

(i.e., it does not remain active until the S1STS

any of the processor interrupt lines (INT0–INT4),

then it must be latched by user logic.

ERRATA

An 80C186EB/80L186EB with a STEPID value of

0001H has the following known errata. A device with

a STEPID of 0001H can be visually identified by the

presence of an ‘‘A’’ alpha character next to the

FPO number. The FPO number location is shown in

Figures 4, 5 and 6.

An 80C186EB/80L186EB with a STEPID value of

0001H or 0002H has the following known errata. A

device with a STEPID of 0002H can be visually iden-

tified by noting the presence of a ‘‘B’’, ‘‘C’’, ‘‘D’’, or

‘‘E’’ alpha character next to the FPO number. The

FPO number location is shown in Figures 4, 5 and 6.

1. A19/ONCE is not latched by the rising edge of

RESIN. A19/ONCE must remain active (LOW) at

all times to remain in the ONCE Mode. Removing

A19/ONCE after RESIN is high will return all out-

put pins to

80C186EB will remain in a reset state.

a driving state, however, the

1. An internal condition with the interrupt controller

can cause no acknowledge cycle on the INTA1

line in response to INT1. This errata only occurs

when Interrupt 1 is configured in cascade mode

and a higher priority interrupt exists. This errata

will not occur consistantly, it is dependent on in-

terrupt timing.

2. During interrupt acknowledge (INTA) bus cycles,

the bus controller will ignore the state of the

READY pin if the previous bus cycle ignored the

state of the READY pin. This errata can only oc-

cur if the Chip-Select Unit is being used. All active

chip-selects must be programmed to use READY

(RDY bit must be programmed to a 1) if wait-

states are required for INTA bus cycles.

REVISION HISTORY

3. CLKOUT will transition off the rising edge of

CLKIN rather than the falling edge of CLKIN. This

This data sheet replaces the following data sheets:

270803-004 80C186EB

270885-003 80C188EB

does not affect any bus timings other than T

4. RESIN has a hysterisis of only 130 mV. It is rec-

ommended that RESIN be driven by a Schmitt

triggered device to avoid processor lockup during

reset using an RC circuit.

270921-003 80L186EB

270920-003 80L188EB

272311-001 SB80C188EB/SB80L188EB

272312-001 SB80C186EB/SB80L186EB

1...56 57 5859

下载PDF

与80C186EB13相关器件

型号	品牌	描述	获取价格	数据表
80C186EB20	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格
80C186EB25	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格
80C186EC	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格
80C186EC13	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格
80C186EC20	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格
80C186EC25	INTEL	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS	获取价格