PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ
E
Figure 34. Hardware Components of the ITP ..... 79
Figure 35. AGTL+ Signal Termination................. 82
Table 19. AGTL+ Signal Groups Ringback
Tolerance Specifications at the
Processor Core....................................35
Figure 36. TCK with Individual Buffering
Scheme...............................................84
Table 20. AGTL+ Overshoot/Undershoot
Guidelines at the Processor Core........37
Figure 37. System Preferred Debug Port
Layout.................................................85
Table 21. 2.5 V Tolerant Signal
Overshoot/Undershoot Guidelines at
the Processor Core..............................38
Figure 38. PWRGOOD Relationship at
Power-On............................................92
Table 22. Signal Ringback Specifications for
2.5 V Tolerant Signal Simulation at the
Processor Core....................................38
TABLES
Table 1. Core Frequency to System Bus
Multiplier Configuration ........................ 12
Table 23. Processor Information ROM Format...43
Table 24. Current Address Read SMBus
Packet..................................................46
Table 2. Core and L2 Voltage Identification
Definition..............................................15
Table 25. Random Address Read SMBus
Packet..................................................46
®
Table 3. Pentium II Xeon™ Processor System
Pin Groups...........................................17
Table 26. Byte Write SMBus Packet...................46
Table 27. Write Byte SMBus Packet...................47
Table 28. Read Byte SMBus Packet...................47
Table 29. Send Byte SMBus Packet...................47
Table 30. Receive Byte SMBus Packet..............47
Table 31. ARA SMBus Packet............................48
Table 32. Command Byte Bit Assignments ........48
Table 33. Thermal Sensor Status Register.........49
®
Table 4. Pentium II Xeon™ Processor Absolute
Maximum Ratings ................................19
Table 5. Voltage Specifications........................... 20
Table 6. Current Specifications...........................21
Table 7. AGTL+ Signal Groups, DC
Specifications at the Processor Core .. 22
Table 8. CMOS, TAP, Clock and APIC Signal
Groups, DC Specifications at the
Processor Core....................................23
Table 34. Thermal Sensor Configuration
Register................................................50
Table 9. SMBus Signal Group, DC Specifications
at the Processor Core..........................23
Table 35. Thermal Sensor Conversion Rate
Register................................................50
®
Table 10. Pentium II Xeon™ Processor Internal
Parameters for the AGTL+ Bus ...........24
Table 36. Thermal Sensor SMBus Addressing on
Table 11. System Bus AC Specifications (Clock)
at the Processor Core..........................25
®
the Pentium II Xeon™ Processor......51
Table 37. Memory Device SMBus Addressing on
Table 12. AGTL+ Signal Groups, System Bus
AC Specifications at the Processor
®
the Pentium II Xeon™ Processor......51
Core .....................................................26
Table 38. Thermal Design Power........................53
Table 13. CMOS, TAP, Clock and APIC Signal
Groups, AC Specifications at the
Table 39. Example Thermal Solution
Performance at Thermal Plate Power of
50 Watts...............................................55
Processor Core....................................26
Table 14. System Bus AC Specifications (Reset
Conditions)...........................................27
Table 40. Signal Listing in Order by Pin
Number ................................................65
Table 15. System Bus AC Specifications (APIC
Clock and APIC I/O) at the Processor
Table 41. Signal Listing in Order by Pin Name ..70
Table 42. Boxed Processor Heatsink
Core .....................................................27
Dimensions ..........................................77
Table 16. System Bus AC Specifications (TAP
Connection) at the Processor Core..... 28
Table 43. Debug Port Pinout Description and
Requirements.......................................80
Table 17. SMBus Signal Group, AC
Table 44. BR[3:0]# Signals Rotating Interconnect,
4-Way System .....................................88
Specifications at the Edge Fingers ...... 29
Table 18. BCLK Signal Quality Specifications for
Simulation at the Processor Core........34
Table 45. BR[3:0]# Signals Rotating Interconnect,
2-Way System .....................................88
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