Datasheet > 7C187-35

7C187-35

更新时间： 2022-11-27 18:13:14

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	145K
描述
64K x 1 Static RAM

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数据手册

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7C187-35 数据手册

CY7C187

Switching Waveforms

Read Cycle No. 2^{[10, 12]}

ACE

HZCE

LZCE

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA OUT

DATA VALID

ICC

SUPPLY

CURRENT

50%

ISB

C187–7

Write Cycle No. 1 (WE Controlled)^[11]

ADDRESS

SCE

PWE

DATA IN

DATA VALID

LZWE

HZWE

HIGH IMPEDANCE

DATA OUT

DATA UNDEFINED

C187–8

Write Cycle No. 2 (CE Controlled)^{[11, 13]}

ADDRESS

SCE

PWE

DATA IN

DATA VALID

HIGH IMPEDANCE

DATA OUT

C187–9

Notes:

12. Address valid prior to or coincident with CE transition LOW.

13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 38-05044 Rev. **

Page 5 of 9

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