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7C187-35 PDF预览

7C187-35

更新时间: 2022-11-27 18:13:14
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 145K
描述
64K x 1 Static RAM

7C187-35 数据手册

 浏览型号7C187-35的Datasheet PDF文件第1页浏览型号7C187-35的Datasheet PDF文件第2页浏览型号7C187-35的Datasheet PDF文件第4页浏览型号7C187-35的Datasheet PDF文件第5页浏览型号7C187-35的Datasheet PDF文件第6页浏览型号7C187-35的Datasheet PDF文件第7页 
CY7C187  
AC Test Loads and Waveforms  
R1 329 Ω  
R1 329 Ω  
(480MIL)  
(480 MIL)  
5V  
OUTPUT  
5V  
OUTPUT  
R2 202 Ω  
(R1 255MIL)  
ALL INPUT PULSES  
90%  
3.0V  
GND  
90%  
10%  
R2 202 Ω  
(R1 255 MIL)  
30 pF  
5 pF  
10%  
5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
5 ns  
C1874  
C1875  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
OUTPUT  
125Ω  
1.73V  
OUTPUT  
1.90V  
Military  
Commercial  
Switching Characteristics Over the Operating Range[6]  
7C187-15  
7C187-20  
Parameter  
Description  
Min.  
15  
3
Max.  
Min.  
20  
5
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
15  
15  
8
20  
20  
8
tOHA  
Output Hold from Address Change  
CE LOW to Data Valid  
CE LOW to Low Z[7]  
tACE  
tLZCE  
3
5
tHZCE  
CE HIGH to High Z[7, 8]  
tPU  
CE LOW to Power Up  
0
0
tPD  
CE HIGH to Power Down  
15  
20  
WRITE CYCLE[9]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
15  
12  
12  
0
20  
15  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tSA  
0
0
tPWE  
tSD  
12  
10  
0
15  
10  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
5
5
tHZWE  
WE LOW to High Z[8]  
7
7
Notes:  
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.  
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05044 Rev. **  
Page 3 of 9  

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