Datasheet > 7C136-15

7C136-15

更新时间： 2022-11-25 14:04:40

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	341K
描述
2Kx8 Dual-Port Static RAM

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数据手册

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7C136-15 数据手册

CY7C132/CY7C136

CY7C142/CY7C146

Switching Waveforms

[20, 21]

Read Cycle No. 1 (Either Port-Address Access)

ADDRESS

OHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

C132-7

[20, 22]

Read Cycle No. 2 (Either Port-CE/OE)

HZCE

ACE

HZOE

DOE

LZOE

LZCE

DATA VALID

DATA OUT

C132-8

Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)

ADDRESS

ADDRESS MATCH

PWE

R/W

INR

VALID

ADDRESS MATCH

ADDRESS

BHA

BUSY

BDD

BLA

DOUT

VALID

DDD

WDD

C132-9

Notes:

20. R/W is HIGH for read cycle.

21. Device is continuously selected, CE = V_ILand OE = V_IL.

22. Address valid prior to or coincident with CE transition LOW.

1...4 5 678 9 10...18

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