CY7C132/CY7C136
CY7C142/CY7C146
[6, 11]
Switching Characteristics Over the Operating Range
(continued)
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
[15]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
45
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
30
30
2
35
35
2
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
HA
0
0
0
SA
25
15
0
30
20
0
30
20
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[10]
R/W LOW to High Z
20
20
25
HZWE
LZWE
[10]
R/W HIGH to Low Z
0
0
0
BUSY/INTERRUPT TIMING
t
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
[16]
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
[16]
BUSY HIGH from CE HIGH
Port Set Up for Priority
5
0
5
0
5
0
[17]
R/W LOW after BUSY LOW
WB
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
30
35
35
WH
35
45
45
BDD
DDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
t
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
WDD
[19]
INTERRUPT TIMING
t
t
t
t
t
t
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
WINS
EINS
INS
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
[16]
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
OINR
EINR
INR
[16]
[16]
Address to INTERRUPT Reset Time
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
OL/IOH, and 30-pF load capacitance.
I
12. AC test conditions use VOH = 1.6V and VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
14.
tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C142/CY7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
19. 52-pin PLCC and PQFP versions only.
6
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