Datasheet > 7C1351-50

7C1351-50

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	185K
描述
128Kx36 Flow-Through SRAM with NoBL TM Architecture

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数据手册

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7C1351-50 数据手册

CY7C1351

Cycle Description Truth Table^{[1, 2, 3, 4, 5, 6]}

Address

used

ADV/

Operation

CEN

BWS

CLK

Comments

Deselected

External

L-H

I/Os three-state following next

recognized clock.

Suspend

L-H

Clock ignored, all operations

suspended.

Begin Read

Begin Write

External

L-H

Address latched.

Valid

Address latched, data presented

two valid clocks later.

Burst Read

Operation

Internal

L-H

Burst Read operation. Previous

access was a Read operation. Ad-

dresses incremented internally in

conjunction with the state of

MODE.

Burst Write

Operation

Internal

Valid

L-H

Burst Write operation. Previous

access was a Write operation. Ad-

dresses incremented internally in

conjunction with the state of

MODE. Bytes written are deter-

mined by BWS

[3:0]

Notes:

1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS

= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BWS

. See Write Cycle Description table for details.

[3:0]

3. The DQ and DP pins are controlled by the current cycle and the OE signal.

4. CEN=1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

1 2 3 456 7 8...13

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