Datasheet > 78P2342JAT-IEL/A07R/F

78P2342JAT-IEL/A07R/F

更新时间： 2023-01-03 07:37:38

品牌	Logo	应用领域
东电化 - TDK		/
页数	文件大小	规格书
37页	458K
描述
Digital Transmission Interface, E-3, PQFP100

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78P2342JAT-IEL/A07R/F 数据手册

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78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

Address Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Sub-Address

SA[1]

Bit 1

Bit 0

Read/

Write

Port Address

Assignment

PA[3]

PA[2]

PA[1]

PA[0]

SA[2]

SA[0]

R/W*

a) PA[3:0] = 0 : Global Registers

Reg.

Sub

Description

Master Control

Interrupt Control

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr

Name

REGEN

<0>

INPOL

<0>

<X>

ENDECB RCLKP

TCLKP

<0>

JAER

<0>

SRST

<0>

TXER

<1>

MSCR

DS3

<X>

(R/W)

<0>

INTC

(R/W)

RXER

<1>

RSVD

Reserved

<0>

b) PA[3:0] = 1-2 : Port-Specific Registers

Reg.

Name

Sub

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr

MDCR

PDTX

<0>

PDRX

<0>

LBO

<1>

LLBKA

<0>

LLBKB

<0>

RLBK

<0>

MON

<0>

TXEN

<1>

Mode Control

(R/W)

STAT

(R/O)

RSVD

JACR

(R/W)

Status Monitor

Reserved

FERR

LOS

TXNW

SGLO

<1>

JAEN

<X>

<1>

<0>

<1>

<0>

ESP[1]

<1>

ESP[0]

<1>

<0>

JABW

<X>

Jitter Attenuator

JASL

JLBK

<X>

<0>

Control

RSVD

Reserved

<0>

Note: Shaded registers in Register Table are reserved for TDK internal use only. Accessing reserved or

undefined registers may cause undesirable operation.

- 7 -

1...4 5 678 9 10...37

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