78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REVISION HISTORY
Revision Date:
Revision Description:
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ENDEC pin addition (pin 15) and default change to ENDEC bit
Changed LBOx pin functionality by adding TXEN & PDTX control
Corrected LPBKx pin description and Intrinsic Transmit Jitter spec.
June 24, 2002
Changed to Preliminary Status
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Added Exposed Pad package option (-IEL) and Lead-free option (/ F)
Updated Receive Jitter Tolerance and Jitter Transfer graphs
Removed SGHI bit definition
Updated Internal Power on Reset description
Added pin type CIT
Updated timing diagrams & e-spec table values
Changed recommended Rx / Tx termination resistor values to 84.5 / 402 ohm respectively
Added Thermal Information section
July 10, 2003
Changed to Final Status
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Updated ENDEC description (pg.4)
Updated RNEGx and RPOSx pin descriptions (pg.14)
Updated DC Characteristics (pg.17)
Updated pull-up & pull-down resistances (pg.18)
Added Loss of Signal timing specs (pg.22)
Updated Transmitter Specification conditions (pg.23)
Updated Transmit Monitor Specifications (pg.28)
Corrected Jitter Transfer BW for JAT disabled (pg.32)
Updated ordering numbers and IC markings (pg.36)
February 9, 2004
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warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation (TSC) reserves the right to make changes in
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TDK Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com
02/09/04 – rev 2.1
©
2004 TDK Semiconductor Corporation
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