100 MS/s, 16-Bit Arbitrary Waveform Generator
Specifications
Specifications are valid for 0 to 55 °C, unless otherwise noted.
Onboard Clock (Internal VCXO)
Sample clock source ........................................ Phase locked to reference clock or derived from onboard
General
VCXO frequency reference.
Frequency accuracy.......................................... 25 ppm
PLL reference clock sources............................. PXI_CLK10, CLK IN, ꢁTSI_7
Number of channels.........................................
1
DAC resolution ................................................. 16 bits
Maximum sampling rate .................................. 100 MS/s
Maximum effective sampling rate
with Interpolation............................................. 400 MS/s
Bandwidth ........................................................ 43 MHz
Output paths..................................................... 1. Main Output Path setting with driver selected Low
Gain Amplifier or the High Gain Amplifier
Digital Data and Control, DDC (optional front panel connector)
Data output signals.......................................... 16 LVDS data lines (ANSI/TIA/EIA-644 compliant)
Start Trigger
Sources ............................................................ PFI <0:3>, PXI_TꢁIG<0:7>, ꢁTSI <0:7>
PXI Star Trigger, Software, Immediate
Modes............................................................... Single, Continuous, Stepped, Burst
2. Direct Path optimized for IF applications
Analog Output
Amplitude range (full scale)
Markers
Destinations ..................................................... PFI <0:1>, PFI <4:5>, PXI_TꢁIG <0:7>, ꢁTSI <0:7>
Quantity............................................................ 1 Marker per Segment
Main output path ............................................. 12 Vpp to 5.64 mVpp (50 Ω load)
Direct path........................................................ 1 Vpp to 0.707 Vpp (50 Ω load)
Offset range ..................................................... 25ꢀ of Amplitude ꢁange
Output impedance............................................ 50 or 75 Ω, software selectable
DC Accuracy
0 to 55 ˚C................................................... 0.4ꢀ of amplitude, 0.05ꢀ of offset 1 mV
Within 10 ˚C of
self-calibration temperature ..................... 0.2ꢀ of amplitude, 0.05ꢀ of offset 500 ΩV
Waveform and Instruction Memory Utilization
8 MB Standard
8,388,608 bytes
32 MB Option
33,554,432 bytes
256 MB Option
268,435,456 bytes
Onboard Memory Size
Output modes................................................... Arbitrary waveform; Arbitrary sequence
Loop count........................................................ 1 to 16,777,215. Burst trigger: unlimited
AC amplitude accuracy ....................................
1.0ꢀ of Amplitude 1 mV at 50 kHz
Memory Limits
8 MB
4,194,176
Samples
32 MB
16,777,088
Samples
256 MB
134,217,600
Samples
Comment
Output filters .................................................... 2. Software selectable seven-pole elliptical analog filter
and finite impulse response (FIꢁ) digital interpolating filter
Arbitrary waveform
Mode maximum
Waveform memory
Arbitrary sequence
Mode maximum
Waveform memory
Arbitrary sequence
Mode maximum
Waveforms
ꢁefer to detailed
specifications for all
trigger modes.
Condition: One or
two segments
in a sequence
Condition: One or
two segments
Passband flatness ............................................
0.25 dB (100 Hz to 40 MHz) for Direct Path
Normalized Passband Flatness, Direct Path
4,194,120
Samples
16,777,008
Samples
134,217,520
Samples
65,000
262,000
418,000
2,097,000
3,354,000
in a sequence
Condition: Waveform
memory is
Arbitrary sequence
Mode maximum
Segments in a sequence
104,000
<4,000 samples.
Power
+3.3 VDC
1.9 A
+5 VDC
2.0 A
+12 VDC
0.46 A
-12 VDC
0.01 A
Total Power
21.9 W
Physical
Front panel connectors
CH0 ............................................................ SMB (Jack)
CLK IN........................................................ SMB (Jack)
PFI 0 ........................................................... SMB (Jack)
PFI 1 ........................................................... SMB (Jack)
ꢁise/fall time.................................................... < 8 ns for Main Output Low Gain Path
Spectral Characteristics Frequency
Direct Path
64 dB
61 dB
Low Gain Path
66 dB
60 dB
71 dBc
Comments
Amplitude -1 dBFS
Measured from DC to
50 MHz
Digital data and control ................................... 68-pin VHDCI Female ꢁeceptacle
Signal to Noise
1 MHz
10 MHz
1 MHz
10 MHz
1 MHz
10 MHz
20 kHz
1 MHz
and Distortion (SINAD)
Spurious Free Dynamic
ꢁange w/ Harmonics
Spurious Free Dynamic
ꢁange w/o Harmonics
Total Harmonic
Environment
76 dBc
Operating temperature (PXI) ............................ 0 to +55 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
Operating temperature (PCI) ............................ 0 to +45 °C
Storage temperature........................................ -25 to +85 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
ꢁelative humidity ............................................. 10 to 90ꢀ, noncondensing (Meets IEC 60068-2-56)
68 dBc
64 dBc
88 dBFS
87 dBFS
91 dBFS
-89 dBFS
-77 dBc (0.014ꢀ) -77 dBc (0.014ꢀ) Amplitude -1 dBFS
Distortion (THD)
-75 dBc
-70 dBc
2nd through 6th
harmonics
Calibration
Self-calibration................................................. Correction for DC gain offset, and timing errors
External calibration interval............................. 2 years
Average Noise Density
Certifications and Compliances
Amplitude Range
Average Noise Density
nV/√Hz dBm/Hz dBfs/Hz
CE Mark compliance
Path
Low gain
High gain
Vp-p
0.1
12
dBm
-16.0
25.6
9
-148
-120
-132.0
-145.6
Note
213
Unless otherwise noted, the following conditions were used for each specification:
A. Analog filter enabled
Sample Clock
B. Interpolation set to maximum allowed factor for a given sample rate
C. Signals terminated with 50Ω
D. Direct path set to 1 Vpk-pk, Low Gain Amplifier Path set to 2 Vpk-pk,
and High Gain Amplifier Path set to 12 Vpk-pk
E. Sample clock set to 100 MS/s
Sources ............................................................ Internal Divide-by-N, Internal High-ꢁesolution, External CLK
IN, External DDC Clk In, PXI star Trigger, PXI_TꢁIG <0:7>,
ꢁTSI <0:7>
Frequency resolution
Divide-by-N................................................ (100 MS/s) / N where 1 ≤ N ≤ 4,194,304
High ꢁesolution ......................................... 1.06 µHz
For detailed specifications on power, environmental, safety, and physical dimensions, please visit
ni.com/products and enter express code: pxi5421 or pci5421
System Phase
Noise Density
System Output
Jitter
Comment
Divide-by-N (PXI)
Divide-by-N (PCI)
High ꢁesolution
-137 dBc/Hz (10 kHz offset)
-137 dBc/Hz (10 kHz offset)
-126 dBc/Hz (10 kHz offset)
< 1.0 ps rms
< 2.0 ps rms
< 4.0 ps rms
10 MHz carrier
National Instruments • Tel: (800) 433-3488 • Fax: (512) 683-9300 • info@ni.com • ni.com 3
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
