Datasheet > 75K62134

75K62134

更新时间： 2024-01-29 16:44:44

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
1页	29K
描述
Microprocessor

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75K62134 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

75K62134 数据手册

Product

Brief

IDT75K52134

IDT75K62134

4.5M and 9M Integrated

IP Co-Processors (IIPC)

with QDR^™Interface

To request the full product brief, please contact your local

IDT Sales Representative or call 1-831-754-4555

DeviceDescription

Introduction

TheIIPCwithasingleQDR™(QuadDataRate)interfaceisintended

toworkwithanyNPUhavinga QDR™lookaside interface suchas the

newIntel®networkprocessors,IXP2400andIXP2800. Multipledevices

includingtheQDR™IIPCcanbeconnectedtothesameQDR™interface.

Each QDR™ IIPC device may be depth expanded up to eight IIPC

devices.

Evolvingnetworkspeedsrequirecriticalfunctionssuchasforwarding

andclassificationtomigratetowardsdedicatedhardwaredevices. The

Integrated IP Co-Processor (IIPC) based on IDT's CAM (Content

AddressableMemory)technologyacceleratessearchfunctionsrequired

forapplications suchas Access ControlLists (ACL), FlowCachingand

Forwarding.

ExternalInterfaces

ThefollowingexternalinterfacesaresupportedbytheQDR™IIPCdevice

IIPCFeatures

◆

128K x 72 (9M) or 64K x 72 (4.5M) Data and Mask cells

◆

SingleQDR™NPUinterface

Full Ternary Content Addressable Memory

◆

- QDR™ Clock Frequency between 90 and 250 MHz

- Supports QDR™burstof2

AdvancedDatabaseManagement

- SelectableDatabases

- Echoclockssupported(CQ,CQ)

CascadingInterface

- ProgrammableWidthperDatabase

- Lookupwidthsfrom32to576bits

- OnlytheselectedDatabaseispowered

◆

- UptoeightIIPCscanbedepthcascadedusingthisscheme

◆

IndirectionSRAM™withstandardZBT®Interface

LookupInstructions

◆

Boundary Scan JTAG Interface (IEEE 1149.1)

- StandardLookup

- Multi-HitLookup

- Multi-DatabaseLookup

- Re-IssueMulti-DatabaseLookup

Figure 1.0 QDR™ IIPC External Interfaces

◆

Maintenance Features

- Aging

- MultiHitInvalidate

- Learn per Database

QDR

Read

Control

Logic

Cascade

Interface

128K x 72 Full

Ternary Content

Addressable Memory

◆

Multi-Context support

◆

Pool of (72-bit) Global Mask Registers (shared across contexts)

◆

In-Band Control and Management

◆

IndirectionSRAM™issupportedthroughaglue-lessZBT®interface

◆

Lowest Power per Application

ZBT

Interface

◆

Synchronous Pipeline Operation

QDR

Write

Control

Logic

◆

Boundary Scan JTAG Interface

◆

1.2V Core Supply

◆

1.5V HSTL I/O Supply

◆

2.5V I/O Supply for ZBT® Indirection SRAM™

◆

35mm x 35mm BGA Package

JTAG Interface

6070 drw04aa

APRIL 2002

DSC-6070/00

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

QDR™ - Quad Data Rate (Trademark of Cypress, IDT, Micron, NEC and Samsung.) All brands or products are the trademarks or registered trademarks of their

respective owners.

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