75232
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS(Cont.)
DRIVER SECTION (VDD=9V, VSS=-9V, VCC=5V)
Output Voltage Level
(Figure. 1)
High
Low
High
Low
VOH
VOL
IIH
VIL=0.8V, RL=3 kΩ
VIH=1.9V, RL=3 kΩ (Note 1)
VIN=5V
6
7.5
V
V
-7.5
-6
10
Input Current Level
(Figure. 2)
μA
mA
mA
mA
Ω
IIL
VIN=0V
-1.6
-19.5
19.5
Short Circuit Output Current High
(Figure. 1)
IOS(H) VIL=0.8V, VOUT=0V (Note 2)
IOS(L) VIH=2.0V, VOUT=0V
-8.5
8.5
-12
12
Low
Output Resistance (Note 3)
ROUT VDD=VSS=VCC=0V, VOUT=-2V~2V
300
RECEIVER SECTION (VDD=9V, VSS=-9V, VCC=5V)
Ta=25°C (Figure. 5)
Ta=0°C ~ 70°C (Figure. 5)
1.75
1.55
0.75
0.5
1.9
0.97
4
2.3
2.3
Positive
VT+
V
Going Threshold Voltage
Input Hysteresis(VT+ - VT-)
Output Voltage Level
Negative
VT-
1.25
V
V
VHYS
VIH=0.75V
Inputs Open
2.6
5
High
Low
High
VOH
VOL
IIH
IOH=-0.5mA
V
V
2.6
VIN=3V, IOL=10mA
VIN=25V
0.2
0.45
8.3
3.6
0.43
-3.6
mA
Input Current Level
(Figure. 5)
VIN=3V
VIN=-25V
VIN=-3V
-8.3
Low
IIL
mA
mA
-0.43
Short-Circuit Output Current
IOS
(Fig. 4)
-3.4
-12
Note. 1. For voltage logic levels, the more positive (less negative) limit is designated as maximum, (e.g. if -10V is a
maximum, the typical value is a more negative voltage).
2: Output short circuit conditions must maintain the total power dissipation below absolute maximum ratings
and the sign is used to indicate direction.
3: Test conditions are those specified by TIA/EIA232-F and as listed above.
SWITCHING CHARACTERISTICS (Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER SECTION (VDD=12V, VSS=-12V, VCC=5V)
Low to High
tPLH
tPHL
tTLH
tTHL
tTLH
tTHL
RL=3 ~ 7 kΩ, CL=15pF
(Figure. 3)
315
75
500
175
100
75
ns
ns
ns
ns
μs
μs
Propagation Delay Time
Transition Time
High to low
Low to High
High to Low
Low to High
High to Low
60
RL=3 ~ 7 kΩ, CL=15pF
40
RL=3 ~ 7 kΩ, CL=2500pF
(Figure. 3, Note)
1.7
1.5
2.5
2.5
RECEIVER SECTION (VDD=12V, VSS=-12V, VCC=5V)
Low to High
High to low
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tTLH
tTHL
107
42
250
150
160
100
350
60
ns
ns
ns
ns
ns
ns
ns
ns
RL=5 kΩ, CL=50pF
RL=1.5 kΩ, CL=15pF
RL=5 kΩ, CL=50pF
RL=1.5 kΩ, CL=15pF
Propagation Delay Time
(Figure. 6)
100
60
175
16
Transition Time
(Figure. 6)
90
175
50
15
Note: Measured points of the output waveform (TIA/EIA-232-F conditions) as below, all unused inputs are tied.
- Low to High level: between -3V and 3V.
- High to Low level: between 3V and -3V.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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