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74VHCT16245ATTR PDF预览

74VHCT16245ATTR

更新时间: 2024-02-29 03:46:18
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器输出元件
页数 文件大小 规格书
10页 251K
描述
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS (NON INVERTED)

74VHCT16245ATTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:48Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.24系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

74VHCT16245ATTR 数据手册

 浏览型号74VHCT16245ATTR的Datasheet PDF文件第2页浏览型号74VHCT16245ATTR的Datasheet PDF文件第3页浏览型号74VHCT16245ATTR的Datasheet PDF文件第4页浏览型号74VHCT16245ATTR的Datasheet PDF文件第5页浏览型号74VHCT16245ATTR的Datasheet PDF文件第6页浏览型号74VHCT16245ATTR的Datasheet PDF文件第7页 
74VHCT16245A  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 4.5 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
V
IH  
IL  
TSSOP  
TUBE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
TSSOP  
74VHCT16245ATTR  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V = 0.9V (MAX.)  
PIN CONNECTION  
OLP  
DESCRIPTION  
The 74VHCT16245A is an advanced high-speed  
CMOS 16-BIT BUS TRANSCEIVER (3-STATE)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
This IC is intended for two-way asynchronous  
communication between data busses; the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the busses are  
effectively isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
All floating bus terminals during High Z State must  
be held HIGH or LOW.  
July 2003  
1/10  

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