Datasheet > 74LVC273-Q100

74LVC273-Q100

更新时间： 2024-02-01 08:49:04

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
16页	715K
描述
Octal D-type flip-flop with reset; positive-edge trigger

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74LVC273-Q100 数据手册

74LVC273-Q100

Octal D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 16 September 2013

Product data sheet

1. General description

The 74LVC273-Q100 has eight edge-triggered, D-type flip-flops with individual Dn inputs

and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset

(clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the

flip-flop. All outputs are forced LOW independent of clock or data inputs by a LOW voltage

level on the MR input.

The device is useful for applications where the true output only is required and the clock

and master reset are common to all storage elements.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 1.2 V to 3.6 V

 Inputs accept voltages up to 5.5 V

 CMOS low power consumption

 Direct interface with TTL levels

 Output drive capability 50  transmission lines at +85 C

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

12 3 4 5 6 7...16

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