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74HCT4351N PDF预览

74HCT4351N

更新时间： 2024-02-25 03:03:28
品牌 Logo 应用领域
恩智浦 - NXP 复用器开关复用器或开关信号电路
页数 文件大小 规格书
17页 139K
描述
8-channel analog multiplexer/demultiplexer with latch

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74HCT4351N 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DIP, DIP20,.3Reach Compliance Code：unknown
风险等级：5.87模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXER
JESD-30 代码：R-PDIP-T20JESD-609代码：e0
信道数量：8功能数量：1
端子数量：20最大通态电阻 (Ron)：225 Ω
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
最大信号电流：0.025 A子类别：Multiplexer or Switches
最大供电电流 (Isup)：0.16 mA标称供电电压 (Vsup)：5 V
表面贴装：NO最长接通时间：75 ns
切换：BREAK-BEFORE-MAKE技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

74HCT4351N 数据手册

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Philips Semiconductors  
Product specification  
8-channel analog  
multiplexer/demultiplexer with latch  
74HC/HCT4351  
The 74HC/HCT4351 are 8-channel analog  
FEATURES  
multiplexers/demultiplexers with three select inputs (S0 to  
S2), two enable inputs (E1 and E2), a latch enable input  
(LE), eight independent inputs/outputs (Y0 to Y7) and a  
common input/output (Z).  
• Wide analog input voltage range:  
± 5 V  
• Low “ON” resistance:  
80 Ω (typ.) at VCC − VEE = 4.5 V  
70 Ω (typ.) at VCC − VEE = 6.0 V  
60 Ω (typ.) at VCC − VEE = 9.0 V  
With E1 LOW and E2 is HIGH, one of the eight switches is  
selected (low impedance ON-state) by S0 to S2. The data  
at the select inputs may be latched by using the active  
LOW latch enable input (LE). When LE is HIGH the latch  
is transparent. When either of the two enable inputs,  
E1 (active LOW) and E2 (active HIGH), is inactive, all 8  
analog switches are turned off.  
• Logic level translation: to enable 5 V logic to  
communicate with ± 5 V analog signals  
• Typical “break before make” built in  
• Address latches provided  
• Output capability: non-standard  
• ICC category: MSI  
VCC and GND are the supply voltage pins for the digital  
control inputs (S0 to S2, LE, E1 and E2). The VCC to GND  
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.  
The analog inputs/outputs (Y0 to Y7, and Z) can swing  
between VCC as a positive limit and VEE as a negative  
limit.  
GENERAL DESCRIPTION  
The 74HC/HCT4351 are high-speed Si-gate CMOS  
devices. They are specified in compliance with JEDEC  
standard no. 7A.  
V
CC − VEE may not exceed 10.0 V.  
For operation as a digital multiplexer/demultiplexer, VEE is  
connected to GND (typically ground).  
QUICK REFERENCE DATA  
VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
HC  
27  
HCT  
35  
tPZH / tPZL  
turn “ON” time E1, E2 or Sn to Vos  
turn “OFF” time E1, E2 or Sn to Vos  
input capacitance  
CL = 15 pF; RL = 1 kΩ; VCC = 5 V  
ns  
ns  
pF  
pF  
t
PHZ / tPLZ  
21  
23  
CI  
3.5  
25  
3.5  
25  
CPD  
CS  
power dissipation capacitance per switch notes 1 and 2  
max. switch capacitance  
independent (Y)  
common (Z)  
5
5
pF  
pF  
25  
25  
Notes  
2. For HC the condition is VI = GND to VCC  
1. CPD is used to determine the dynamic power  
For HCT the condition is VI = GND to VCC − 1.5 V  
dissipation (PD in µW):  
PD = CPD × VCC2 × fi +∑ {(CL+ CS) × VCC2 × fo}  
where:  
ORDERING INFORMATION  
fi = input frequency in MHz  
See “74HC/HCT/HCU/HCMOS Logic Package  
Information”.  
fo = output frequency in MHz  
CL = output load capacitance in pF  
CS = max. switch capacitance in pF  
∑ {(CL+ CS) × VCC2 × fo} = sum of outputs  
VCC = supply voltage in V  
December 1990  
2
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