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74HC4046ADB

更新时间： 2024-01-22 05:13:12

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
34页	470K
描述
Phase-locked-loop with VCO

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技术参数
数据手册

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74HC4046ADB 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.14	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.1 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

74HC4046ADB 数据手册

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with VCO

74HC/HCT4046A

provided at pin 10 (DEM_OUT). In contrast to conventional

techniques where the DEM_OUTvoltage is one threshold

voltage lower than the VCO input voltage, here the

DEM_OUTvoltage equals that of the VCO input. If

DEM_OUTis used, a load resistor (R_S) should be connected

from DEM_OUTto GND; if unused, DEM_OUTshould be left

open. The VCO output (VCO_OUT) can be connected

directly to the comparator input (COMP_IN), or connected

via a frequency-divider. The VCO output signal has a duty

factor of 50% (maximum expected deviation 1%), if the

VCO input is held at a constant DC level. A LOW level at

the inhibit input (INH) enables the VCO and demodulator,

while a HIGH level turns both off to minimize standby

power consumption.

FEATURES

• Low power consumption

• Centre frequency of up to 17 MHz (typ.) at V_CC= 4.5 V

• Choice of three phase comparators: EXCLUSIVE-OR;

edge-triggered JK flip-flop;

edge-triggered RS flip-flop

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF keying and for low

standby power consumption

• Minimal frequency drift

• Operating power supply voltage range:

VCO section 3.0 to 6.0 V

digital section 2.0 to 6.0 V

The only difference between the HC and HCT versions is

the input level specification of the INH input. This input

disables the VCO section. The sections of the comparator

are identical, so that there is no difference in the

SIG_IN(pin 14) or COMP_IN(pin 3) inputs between the HC

and HCT versions.

• Zero voltage offset due to op-amp buffering

• Output capability: standard

• I_CCcategory: MSI.

GENERAL DESCRIPTION

Phase comparators

The 74HC/HCT4046A are high-speed Si-gate CMOS

devices and are pin compatible with the “4046” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The signal input (SIG_IN) can be directly coupled to the

self-biasing amplifier at pin 14, provided that the signal

swing is between the standard HC family input logic levels.

Capacitive coupling is required for signals with smaller

swings.

The 74HC/HCT4046A are phase-locked-loop circuits that

comprise a linear voltage-controlled oscillator (VCO) and

three different phase comparators (PC1, PC2 and PC3)

with a common signal input amplifier and a common

comparator input.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network. The signal and

comparator input frequencies (f_i) must have a 50% duty

factor to obtain the maximum locking range. The transfer

characteristic of PC1, assuming ripple (f_r= 2f_i) is

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to

small voltage signals. A self-bias input circuit keeps small

voltage signals within the linear region of the input

amplifiers. With a passive low-pass filter, the “4046A”

forms a second-order loop PLL. The excellent VCO

linearity is achieved by the use of linear op-amp

techniques.

suppressed, is: V_DEMOUT

^CC(φ

– φ_COMPIN)

SIGIN

----------

where V_DEMOUTis the demodulator output at pin 10;

_DEMOUT= V_PC1OUT(via low-pass filter).

V_CC

The VCO requires one external capacitor C1 (between

C1_Aand C1_B) and one external resistor R1 (between

R₁and GND) or two external resistors R1 and R2

(between R₁and GND, and R₂and GND). Resistor R1

and capacitor C1 determine the frequency range of the

VCO. Resistor R2 enables the VCO to have a frequency

offset if required.

The phase comparator gain is:K_p

(V ⁄ r) .

----------

The average output voltage from PC1, fed to the VCO

input via the low-pass filter and seen at the demodulator

output at pin 10 (V_DEMOUT), is the resultant of the phase

differences of signals (SIG_IN) and the comparator input

(COMP_IN) as shown in Fig.6. The average of V_DEMOUTis

equal to ¹⁄₂V_CCwhen there is no signal or noise at

SIG_INand with this input the VCO oscillates at the centre

frequency (f_o). Typical waveforms for the PC1 loop locked

at f_oare shown in Fig.7.

The high input impedance of the VCO simplifies the design

of low-pass filters by giving the designer a wide choice of

resistor/capacitor ranges. In order not to load the low-pass

filter, a demodulator output of the VCO input voltage is

1997 Nov 25

123 4 5 6 7...34

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与74HC4046ADB相关器件

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74HC4046ADB,118	NXP	74HC(T)4046A - Phase-locked-loop with VCO SSOP1 16-Pin	获取价格
74HC4046ADB-T	NXP	IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-338-1, SSOP-16, PLL or Frequency Synthesis Circu	获取价格
74HC4046AD-T	NXP	IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-109, SO-16, PLL or Frequency Synthesis Circuit	获取价格
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74HC4046AN,652	NXP	74HC(T)4046A - Phase-locked-loop with VCO DIP 16-Pin	获取价格
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