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74HC194D,652 PDF预览

74HC194D,652

更新时间: 2024-02-02 00:06:48
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 75K
描述
74HC(T)194 - 4-bit bidirectional universal shift register SOP 16-Pin

74HC194D,652 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.17
其他特性:HOLD MODE计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4负载电容(CL):50 pF
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:24000000 Hz
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):44 ns认证状态:Not Qualified
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE最小 fmax:20 MHz
Base Number Matches:1

74HC194D,652 数据手册

 浏览型号74HC194D,652的Datasheet PDF文件第4页浏览型号74HC194D,652的Datasheet PDF文件第5页浏览型号74HC194D,652的Datasheet PDF文件第6页浏览型号74HC194D,652的Datasheet PDF文件第7页浏览型号74HC194D,652的Datasheet PDF文件第8页浏览型号74HC194D,652的Datasheet PDF文件第9页 
Philips Semiconductors  
Product specification  
4-bit bidirectional universal shift register  
74HC/HCT194  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.8 Waveforms showing the master reset (MR)  
pulse width, the master reset to output (Qn)  
propagation delays and the master reset to  
clock (CP) removal time.  
Fig.7 Waveforms showing the clock (CP) to  
output (Qn) propagation delays, the clock  
pulse width, the output transition times and  
the maximum clock frequency.  
The shaded areas indicate when the input is permitted to  
change for predictable output performance.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.10 Waveforms showing the set-up and hold  
times from the mode control inputs (Sn) to  
the clock input (CP).  
The shaded areas indicate when the input is permitted to  
change for predictable output performance.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
Fig.9 Waveforms showing the set-up and hold  
times from the data inputs (Dn, DSR and  
DSL) to the clock (CP).  
December 1990  
10  

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