Datasheet > 74FCT388915T15JG

74FCT388915T15JG

更新时间： 2022-09-25 09:52:17

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
10页	154K
描述
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

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数据手册

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74FCT388915T15JG 数据手册

IDT74FCT388915T

3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)

COMMERCIALTEMPERATURERANGE

PINCONFIGURATION

GND

28 27 26

VCC

25 Q/2

FEEDBK

REF_SEL

SYNC(0)

VCC(AN)

VCC

OE/RST

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

Q/2

GND

23 Q3

VCC

GND

LOCK

GND(AN)

GND

LOCK

GND(AN)

SYNC(1)

FREQ_SEL

GND

PLL_EN

GND

12 13 14 15 16 17 18

VCC

SSOP

PLCC

TOP VIEW

PINDESCRIPTION

Pin Name

SYNC(0)

SYNC(1)

REF_SEL

FREQ_SEL

FEEDBACK

I/O

Description

Referenceclockinput

Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)

Selectsbetween÷1and÷2frequencyoptions(refertofunctionalblockdiagram)

Feedbackinputtophasedetector

Inputforexternalloopfilterconnection

Q0-Q4

Clockoutput

Invertedclockoutput

Clock output (2 x Q frequency)

Q/2

Clock output (Q frequency ÷ 2)

LOCK

Indicates phase lock has been achieved (HIGH when locked)

OE/RST

Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in

HIGH impedance.

PLL_EN

Disablesphase-lockforlowfrequencytesting(refertofunctionalblockdiagram)

123 4 5 6 7...10

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